公开(公告)号：US07626914B2

公开(公告)日：2009-12-01

申请号：US11446301

申请日：2006-06-05

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B7/00

CPC分类号： G11B7/005 ,  G11B7/0053 ,  G11B7/0065 ,  G11B7/00781 ,  G11B2007/00653

摘要： An XY array of sync bits and information bits is recorded in a recording medium through the use of holography. The sync bits are in parallel Y-direction-extending groups having an X-direction minimum inversion interval of 2 or more. The information bits are placed between the parallel Y-direction-extending groups of the sync bits. One of the parallel Y-direction-extending groups of the sync bits and ones of the information bits neighboring said one of the parallel Y-direction-extending groups of the sync bits are scanned to reproduce a Y-direction sync bit sequence and at least one Y-direction information bit sequence. The reproduced Y-direction sync bit sequence is re-sampled through the use of a digital phase locked loop to obtain corrected Y-direction sync bit frequency and phase. The Y-direction information bit sequence is re-sampled in response to the corrected Y-direction sync bit frequency and phase. The Y direction is vertical, horizontal, or halfway therebetween.

摘要翻译： 同步位和信息位的XY阵列通过使用全息记录在记录介质中。 同步位是具有2个或更多个X方向最小反转间隔的并行Y方向延伸组。 信息位置于同步位的并行Y方向扩展组之间。 扫描同步位的并行Y方向扩展组之一以及与同步位的并行Y方向扩展组之间的所述一个相邻的信息位之一，以再现Y方向同步位序列，并至少 一个Y方向信息比特序列。 通过使用数字锁相环对重放的Y方向同步位序列进行重新采样，以获得校正的Y方向同步位频率和相位。 响应于校正的Y方向同步位频率和相位来重新采样Y方向信息比特序列。 Y方向垂直，水平或中间。

公开(公告)号：US07593312B2

公开(公告)日：2009-09-22

申请号：US11354900

申请日：2006-02-16

申请人： Junichiro Tonami ,  Takayuki Ohki

发明人： Junichiro Tonami ,  Takayuki Ohki

IPC分类号： G11B7/00

CPC分类号： G11B20/1403 ,  H04L7/048

摘要： An information signal is read from a recording medium to generate a reproduced signal. A sync detector detects a sync signal in the reproduced signal on a pattern search basis during operation in a direct mode. The sync detector sets a detection window and detects a sync signal in the reproduced signal in the detection window during operation in an inertia mode. A special pattern signal in the reproduced signal is detected and counted to generate a count result. The count result is reset in response to detection of a first special signal in the reproduced signal. A detection flag is generated in cases where a second special signal in the reproduced signal is detected when the count result denotes a last sector in a block of the reproduced signal. The sync detector changes its operation from the inertia mode to the direct mode when the detection flag is generated.

摘要翻译： 从记录介质读取信息信号以产生再现信号。 在直接模式下，同步检测器在模式搜索的基础上检测再现信号中的同步信号。 同步检测器设置检测窗口，并且在惯性模式下操作期间检测检测窗口中再现信号中的同步信号。 检测并计数再生信号中的特殊图案信号，生成计数结果。 响应于再现信号中的第一特殊信号的检测，计数结果被复位。 当计数结果表示再现信号的块中的最后一个扇区时，在再现信号中检测到第二特殊信号的情况下产生检测标志。 当产生检测标志时，同步检测器将其操作从惯性模式改变为直接模式。

公开(公告)号：US07123560B2

公开(公告)日：2006-10-17

申请号：US10634892

申请日：2003-08-06

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B7/00

CPC分类号： G11B20/10037 ,  G11B7/0037 ,  G11B20/1403 ,  H03L7/0812 ,  H03L7/085

摘要： In a PLL circuit, a phase error of a reproduced signal is extracted in either a way based on a zero-cross timing or a way based on a self-running timing. A decision is made as to whether the reproduced signal is in a continuous-wave interval where an inversion period of the reproduced signal remains constant or in a random-wave interval where the inversion period of the reproduced signal varies at random. When the reproduced signal is in a continuous-wave interval, a phase error is extracted on the self-running-timing basis. When the reproduced signal is in a random-wave interval, a phase error is extracted on the zero-cross-timing basis. A continuous-wave interval may be replaced by a specified-pattern repetition interval where the inversion period of the reproduced signal changes in accordance with a repetition of a specified pattern.

摘要翻译： 在PLL电路中，以基于零交叉定时或基于自运行定时的方式来提取再现信号的相位误差。 决定再现信号是否处于再现信号的反转周期保持恒定的连续波间隔中，或重放信号的反转周期随机变化的随机波间隔。 当再现信号处于连续波间隔时，在自运行定时的基础上提取相位误差。 当再现信号处于随机波间隔时，在零交叉定时的基础上提取相位误差。 连续波间隔可以由指定图案重复间隔代替，其中再现信号的反转周期根据指定图案的重复而改变。

公开(公告)号：US06661761B2

公开(公告)日：2003-12-09

申请号：US09849981

申请日：2001-05-08

申请人： Atsushi Hayami ,  Junichiro Tonami

发明人： Atsushi Hayami ,  Junichiro Tonami

IPC分类号： G11B700

CPC分类号： G11B20/10212 ,  G11B7/005 ,  G11B7/007 ,  G11B7/0956 ,  G11B7/24085 ,  G11B20/10 ,  G11B20/10009 ,  G11B20/18 ,  H03M13/41 ,  H03M13/6331 ,  H04L1/0054 ,  H04L25/03057 ,  H04L2025/03369 ,  H04L2025/0349

摘要： A resampling DPLL estimates a signal outputted from a pickup through an AGC and outputs a signal of the estimation result. A transversal filter in an adaptive equalizing circuit equalizes in waveform the signal outputted from the resampling DPLL. An error signal is detected from the equalized waveform outputted from the transversal filter. The error signal is fed back to the transversal filter so as to control the transversal filter such that the error signal becomes minimum.

公开(公告)号：US06295316B1

公开(公告)日：2001-09-25

申请号：US09081671

申请日：1998-05-20

申请人： Junichiro Tonami ,  Takashi Kiyofuji

发明人： Junichiro Tonami ,  Takashi Kiyofuji

IPC分类号： H03H740

CPC分类号： H04W52/30 ,  G11B20/10009 ,  G11B20/10425 ,  G11B20/22 ,  H03L7/091 ,  H03M7/4006 ,  H03M13/23 ,  H03M13/2903 ,  H03M13/2993 ,  H03M13/6356 ,  H03M13/6362 ,  H04B7/2628 ,  H04B10/25754 ,  H04J13/0077 ,  H04J13/16 ,  H04L1/0066 ,  H04L1/0068 ,  H04L25/03038 ,  H04L25/497 ,  H04L51/04 ,  H04L51/28 ,  H04L51/38 ,  H04L65/1006 ,  H04L65/1016 ,  H04N19/109 ,  H04N19/139 ,  H04N19/625 ,  H04N19/91 ,  H04W4/12 ,  H04W4/14 ,  H04W8/26 ,  H04W72/042 ,  H04W76/12 ,  H04W88/085 ,  Y10S370/906 ,  Y10S370/907

摘要： An automatic equalization system includes an analog-to-digital converter for periodically sampling an analog signal representative of digital information in response to a sampling clock signal, and for converting every sample of the analog signal into a corresponding digital sample to convert the analog signal into a corresponding digital signal. A first device operates for detecting a phase error of the sampling clock signal in response to a correlation between samples of the digital signal generated by the analog-to-digital converter. A second device operates for controlling a frequency of the sampling clock signal in response to the phase error detected by the first device. A variable filter operates for subjecting the digital signal generated by the analog-to-digital converter to a variable filtering process to convert the digital signal generated by the analog-to-digital converter into a filtering-resultant signal. The filtering process corresponds to a waveform equalization process. A third device operates for detecting an amplitude error of the digital signal generated by the analog-to-digital converter in response to a correlation between samples of the filtering-resultant signal generated by the variable filter. A fourth device operates for controlling the filtering process implemented by the variable filter in response to the amplitude error detected by the third device. The analog-to-digital converter, the first device, and the second device compose a phase locked loop while the variable filter, the third device, and the fourth device compose an amplitude error correcting loop separate from the phase locked loop.

摘要翻译： 一种自动均衡系统包括一个模数转换器，用于响应采样时钟信号对表示数字信息的模拟信号进行周期性采样，并将模拟信号的每个样本转换成相应的数字样本，以将模拟信号转换为 相应的数字信号。 响应于由模数转换器产生的数字信号的采样之间的相关性，第一装置用于检测采样时钟信号的相位误差。 第二装置用于响应于由第一装置检测到的相位误差来控制采样时钟信号的频率。 可变滤波器用于对由模拟 - 数字转换器产生的数字信号进行可变滤波处理，以将由模数转换器产生的数字信号转换为滤波结果信号。 滤波处理对应于波形均衡处理。 第三装置用于响应于由可变滤波器产生的滤波结果信号的采样之间的相关性，检测由模数转换器产生的数字信号的振幅误差。 第四装置用于响应于由第三装置检测到的振幅误差来控制由可变滤波器实现的滤波处理。 模数转换器，第一器件和第二器件组成锁相环，而可变滤波器，第三器件和第四器件构成与锁相环分离的幅度误差校正回路。

公开(公告)号：US6061395A

公开(公告)日：2000-05-09

申请号：US960145

申请日：1997-10-29

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B20/10 ,  H03H15/00 ,  H03H17/02 ,  H04B3/06 ,  H04L25/03 ,  H03H7/30

CPC分类号： H04L25/03038 ,  G11B20/10009 ,  H04L2025/03369 ,  H04L2025/03477

摘要： A waveform equalizer prevents the delay of coefficient convergence due to the characteristics of a reproduced signal or the coefficient divergence due to an increase in determined errors. The waveform equalizer constituted by a transversal filter suppresses inter-symbol interferences of a transmitted digital information signal by multiplying the digital information signal and delayed signals thereof by tab coefficients and adding the multiplication results. The waveform equalizer comprises a virtual determination circuit for virtually determining the most plausible digital information from the output of the transversal filter, an error calculation circuit for providing an amplitude error based on the virtual determination result, a retaining and selecting circuit for retaining and selecting the digital information signal and the delayed output thereof, and an updating circuit for multiplying the output from the error calculation circuit by the outputs from the retaining and selecting circuit and to thereby update tab coefficients, wherein the virtual determination circuit virtually determines the value of a most plausible digital information signal by detecting a peak and utilizing the correlationship between signal components of the digital information signal.

摘要翻译： 波形均衡器防止由于再现信号的特性或由于确定的误差的增加而导致的系数偏差引起的系数收敛的延迟。 由横向滤波器构成的波形均衡器通过将数字信息信号及其延迟信号乘以制表系数并将相乘结果相加来抑制所发送的数字信息信号的符号间干扰。 波形均衡器包括用于从横向滤波器的输出虚拟地确定最合理数字信息的虚拟确定电路，用于基于虚拟确定结果提供幅度误差的误差计算电路，用于保持和选择 数字信息信号及其延迟输出;以及更新电路，用于将来自误差计算电路的输出乘以保持和选择电路的输出，从而更新标签系数，其中虚拟确定电路虚拟地确定最大值 通过检测峰值并利用数字信息信号的信号分量之间的相关性来生成合理的数字信息信号。

公开(公告)号：US07542385B2

公开(公告)日：2009-06-02

申请号：US10538488

申请日：2003-12-03

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B7/0045

CPC分类号： G11B7/0945 ,  G11B7/13925 ,  G11B7/13927

摘要： An optical disk unit capable of correcting a spherical aberration without using special patterns is provided. Also provided is an aberration correcting method used for such an optical disk unit. An objective lens 7 is moved along an optical axis by a predetermined distance from an in-focus position in a first direction, and then, is moved by the predetermined distance from the in-focus position in a second direction that is opposite to the first direction. In each of the objective lens moved states, a random signal having a plurality of amplitudes and periods is reproduced from an optional area of an information recording layer 12 of an optical disk 11. A servo circuit 10 extracts a specific portion having a specific amplitude or period from the reproduced random signal in each of the objective lens moved states, finds a first amplitude value and second amplitude value in the specific portions, and controls an aberration corrector 6 so that the difference between the first amplitude value and the second amplitude value approaches zero.

摘要翻译： 提供了能够在不使用特殊图案的情况下校正球面像差的光盘单元。 还提供了用于这种光盘单元的像差校正方法。 物镜7沿着光轴沿第一方向从对焦位置移动预定距离，然后在与第一方向相反的第二方向上从对焦位置移动预定距离 方向。 在每个物镜移动状态下，从光盘11的信息记录层12的可选区域再现具有多个幅度和周期的随机信号。伺服电路10提取具有特定幅度的特定部分或 在每个物镜移动状态下的再现的随机信号的周期中，在特定部分中找到第一幅度值和第二幅度值，并且控制像差校正器6，使得第一幅度值和第二幅度值之间的差值接近 零。

公开(公告)号：US07423949B2

公开(公告)日：2008-09-09

申请号：US11193341

申请日：2005-08-01

申请人： Junichiro Tonami ,  Yuuki Fujiwara

发明人： Junichiro Tonami ,  Yuuki Fujiwara

IPC分类号： G11B7/00

CPC分类号： G11B20/1426 ,  G11B20/1833 ,  G11B2020/1272 ,  G11B2020/1288 ,  G11B2020/1863 ,  G11B2220/2541

摘要： A signal of a run-length-limited code is read out from a recording medium. The read-out signal is converted into a reproduced digital signal. A decoder subjects the reproduced digital signal to first decoding different from run length decoding to get a first decoded signal. Information bit streams are generated from the first decoded signal. The information bit streams are different in timing by 1-bit-correpsonding intervals. Run length decoders subject the information bit streams to run length decoding to get run-length-decoded bit streams respectively. Each of the run-length-decoded bit streams undergoes one of error correction and error detection. A decision is made as to which of the run-length-decoded bit streams is the smallest in error number on the basis of results of the one of error correction and error detection. The run-length-decoded bit stream being the smallest in error number is selected and outputted as a likeliest information bit stream.

摘要翻译： 从记录介质读出游程长度限制代码的信号。 读出信号被转换成再现的数字信号。 解码器对再现的数字信号进行与游程长度解码不同的第一解码以获得第一解码信号。 从第一解码信号生成信息比特流。 信息比特流在时间上是不同的，通过1位相关的间隔。 运行长度解码器对信息比特流进行运行长度解码以分别获得游程长度解码的比特流。 每个游程长度解码的比特流经历纠错和错误检测之一。 根据错误校正和错误检测的结果，作出关于哪个运行长度解码的比特流在错误数中最小的决定。 作为最差信息比特流，选择并输出错误编号中最小的游程长度解码比特流。

公开(公告)号：US06836456B2

公开(公告)日：2004-12-28

申请号：US09903566

申请日：2001-07-13

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B576

CPC分类号： G11B20/10083 ,  G11B7/005 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10111 ,  G11B20/22

摘要： A first signal is read from a first track of a recording medium. A second signal is read from a second track of the recording medium which neighbors the first track. A filter processes the second signal into a filtering-resultant signal according to a controllable filtering characteristic. A first subtracter operates for subtracting the filtering-resultant signal from the first signal to generate a subtraction-resultant signal. A peak detector generates peak-point information representing a timing at which the level represented by the first signal peaks. A temporary decision circuit implements a temporary decision about the subtraction-resultant signal. A second subtracter generates an error signal indicative of a difference between the subtraction-resultant signal and a signal representative of the result of the temporary decision at a timing equal to the timing represented by the peak-point information. The filtering characteristic of the filter is controlled in response to the error signal.

摘要翻译： 从记录介质的第一轨道读取第一信号。 从与第一轨道相邻的记录介质的第二轨道读取第二信号。 滤波器根据可控滤波特性将第二信号处理成滤波结果信号。 第一减法器用于从第一信号中减去滤波结果信号以产生减法结果信号。 峰值检测器产生表示由第一信号峰值表示的电平的定时的峰值点信息。 临时判定电路对减法结果信号进行临时判定。 第二减法器在等于由峰值点信息表示的定时的定时产生指示减法结果信号和表示临时判定结果的信号之间的差的误差信号。 滤波器的滤波特性根据误差信号进行控制。

公开(公告)号：US06768706B1

公开(公告)日：2004-07-27

申请号：US09427079

申请日：1999-10-26

申请人： Junichiro Tonami

发明人： Junichiro Tonami

IPC分类号： G11B509

CPC分类号： G11B20/1024 ,  G11B20/10027 ,  G11B20/10222 ,  G11B20/10444 ,  G11B2220/2537

摘要： A plurality of cross detectors have predetermined threshold levels different from each other. Each cross detector increments a count value when the reproduced signal crosses over its threshold level and generates the accumulated count value as a cross count value. Upon the cross count value agreeing with a common reference value, each comparator sends the coincidence signal to an OR circuit. The OR circuit produces a reset pulse in response to a first-arriving coincidence signal. The reset pulse is supplied to each cross detector to reset the cross count values of all of cross detectors and is also supplied to a down counter to reset it. When the cross count value becomes a predetermined value, an error signal is produced based on a deviation of the bit clock count value relative to a proper value so as to correct the deviation. The frequency control is performed based on the produced error signal.

摘要翻译： 多个交叉检测器具有彼此不同的预定阈值水平。 每个交叉检测器在再现信号超过其阈值电平时递增计数值，并产生累加计数值作为交叉计数值。 当交叉计数值与公共参考值一致时，每个比较器将符合信号发送到或电路。 OR电路响应于第一到达符合信号产生复位脉冲。 复位脉冲被提供给每个交叉检测器以复位所有交叉检测器的交叉计数值，并且还被提供给向下计数器以将其复位。 当交叉计数值变为预定值时，基于位时钟计数值相对于适当值的偏差产生误差信号，以便校正偏差。 基于产生的误差信号进行频率控制。