公开(公告)号：US06893154B2

公开(公告)日：2005-05-17

申请号：US10080037

申请日：2002-02-19

申请人： Spencer M. Gold ,  Claude R. Gauthier ,  Brian W. Amick ,  Kamran Zarrineh ,  Steven R. Boyle

发明人： Spencer M. Gold ,  Claude R. Gauthier ,  Brian W. Amick ,  Kamran Zarrineh ,  Steven R. Boyle

IPC分类号： G01K1/02 ,  G01K7/00 ,  G01K7/01 ,  G01K7/32 ,  G01K11/00

CPC分类号： G01K7/01 ,  G01K2215/00

摘要： An apparatus and method are provided for sensing a physical stimulus of an integrated circuit. The apparatus and method allow for accurate die temperature measurements of the integrated circuit and are able to provide a highly accurate die temperature measurement without the need for an independent voltage source or current source.

摘要翻译： 提供了一种用于感测集成电路的物理刺激的装置和方法。 该装置和方法允许集成电路的精确的管芯温度测量，并且能够提供高精度的管芯温度测量，而不需要独立的电压源或电流源。

公开(公告)号：US06996491B2

公开(公告)日：2006-02-07

申请号：US10079476

申请日：2002-02-19

申请人： Spencer M. Gold ,  Claude R. Gauthier ,  Steven R. Boyle ,  Kenneth A. House ,  Joseph Siegel

发明人： Spencer M. Gold ,  Claude R. Gauthier ,  Steven R. Boyle ,  Kenneth A. House ,  Joseph Siegel

IPC分类号： G01K1/08

CPC分类号： G06F1/206

摘要： A system and method are provided for sensing a physical stimulus of an integrated circuit. The system and method operate with one or more active thermal sensors embedded in the die of an integrated circuit to provide highly accurate die temperature measurements. The system and method are able to monitor and control the die temperature of the integrated circuit to avoid an integrated circuit malfunction due to an undesirable temperature condition.

公开(公告)号：US07797596B2

公开(公告)日：2010-09-14

申请号：US11861403

申请日：2007-09-26

申请人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

发明人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

IPC分类号： G11C29/00

CPC分类号： G01R31/3187

摘要： A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

摘要翻译： 一种用于测试在电子系统中实现的集成电路的方法。 该方法包括在离线状态下放置在操作系统（例如，计算机系统）中实现的集成电路（或其部分）。 设置集成系统的电参数（例如，电压，时钟频率等），并且进行内置自检（BIST）。 记录在BIST期间发生的任何故障。 然后针对电参数的多个预定值中的每一个重复测试，记录发生的任何故障。 一旦测试完成，则为每个预定值确定故障率/范围。

公开(公告)号：US5499445A

公开(公告)日：1996-03-19

申请号：US226920

申请日：1994-04-13

申请人： Steven R. Boyle ,  Robert J. Proebsting ,  William H. Herndon

发明人： Steven R. Boyle ,  Robert J. Proebsting ,  William H. Herndon

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/66 ,  H05K3/36

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/49 ,  H01L2223/6638 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias are placed near conductive vias to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals (e.g. CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

摘要翻译： 公开了一种采用新颖的屏蔽技术来提高封装的高频性能的多层封装。 屏蔽通孔放置在导电通孔附近，以产生具有可控特性阻抗的双线传输线。 受控的传输线路阻抗可减少由于电感耦合引起的线路阻抗变化和接地反弹引起的信号反射。 在垂直和水平方向引入了相反的极性屏蔽技术，以减少信号之间的噪声的电容耦合，并提供抗差分电源噪声的抗扰度。 位于浮动屏蔽平面之间的信号层提供对非共模噪声耦合的抗扰度。 对于具有不同类型信号（例如CMOS和TTL和ECL型信号）的集成电路，封装产生电隔离区，以显着降低具有不同信号类型的电路之间的噪声耦合。

公开(公告)号：US4990996A

公开(公告)日：1991-02-05

申请号：US134921

申请日：1987-12-18

申请人： Niraj Kumar ,  Steven R. Boyle

发明人： Niraj Kumar ,  Steven R. Boyle

IPC分类号： H01L23/485 ,  H01L23/498 ,  H01L23/50

CPC分类号： H01L24/06 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19043

摘要： A technique is disclosed for manufacturing an integrated circuit die which is capable of being packaged in any of two or more different package types having different arrangements of bonding posts. The circuit is laid out with redundant pads located at different places on the die so that one pad in each pair of redundant pads is accessible for bonding with posts in one package type, while the other pad in each pair of redundant pads is accessible for bonding with posts in another package type. Illustrative layouts are shown whereby various types of pads, e.g., power pads, signal input pads, signal output pads and bidirectional I/O pads, may be made redundant.

摘要翻译： 公开了一种用于制造集成电路管芯的技术，其能够以具有不同布置的接合柱的两种或多种不同的封装类型中的任何一种封装。 该电路布置有位于管芯上不同位置的冗余焊盘，使得每对冗余焊盘中的一个焊盘可访问，用于与一个封装类型的焊盘结合，而每对冗余焊盘中的另一个焊盘可用于焊接 在另一个包类型的帖子。 示出了示例性布局，由此可以使各种类型的焊盘，例如电源焊盘，信号输入焊盘，信号输出焊盘和双向I / O焊盘成为冗余的。

公开(公告)号：US20090083598A1

公开(公告)日：2009-03-26

申请号：US11861403

申请日：2007-09-26

申请人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

发明人： Anand Dixit ,  Raymond A. Heald ,  Steven R. Boyle

IPC分类号： G01R31/3187 ,  G06F11/27

CPC分类号： G01R31/3187

摘要： A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.

摘要翻译： 一种用于测试在电子系统中实现的集成电路的方法。 该方法包括在离线状态下放置在操作系统（例如，计算机系统）中实现的集成电路（或其部分）。 设置集成系统的电参数（例如，电压，时钟频率等），并且进行内置自检（BIST）。 记录在BIST期间发生的任何故障。 然后针对电参数的多个预定值中的每一个重复测试，记录发生的任何故障。 一旦测试完成，则为每个预定值确定故障率/范围。

公开(公告)号：US06943436B2

公开(公告)日：2005-09-13

申请号：US10345016

申请日：2003-01-15

申请人： Sergiu Radu ,  Steven R. Boyle

发明人： Sergiu Radu ,  Steven R. Boyle

IPC分类号： H01L23/552 ,  H05K1/02 ,  H01L23/02

CPC分类号： H01L23/552 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H01L2224/0401

摘要： An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a circuit board.

摘要翻译： 集成电路封装包括具有EMI抑制特征的盖子。 盖可以包括适于联接电路板的接地平面的多个突起。

公开(公告)号：US5338970A

公开(公告)日：1994-08-16

申请号：US36564

申请日：1993-03-24

申请人： Steven R. Boyle ,  Robert J. Proebsting ,  William H. Herndon

发明人： Steven R. Boyle ,  Robert J. Proebsting ,  William H. Herndon

IPC分类号： H01L23/12 ,  H01L23/498 ,  H01L23/66 ,  H01L25/04 ,  H01L23/02 ,  H01L23/16

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/49 ,  H01L2223/6638 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A multi-layered package is disclosed that employs novel shielding techniques to improve high frequency performance of the package. Shield vias are placed near conductive vias to create a two-wire transmission line with controllable characteristic impedance. Controlled transmission line impedance reduces signal reflection due to line impedance variations and ground bounce due to inductive coupling. Opposite polarity shielding technique is introduced in vertical as well as horizontal directions to reduce capacitive coupling of noise between signals and provide immunity against differential power supply noise. Signal layers disposed half way between floating shield planes provided immunity against non-common mode noise coupling. For integrated circuits with varying types of signals (e.g. CMOS and TTL and ECL type signals), the package creates electrically isolated zones to drastically reduce noise coupling between the circuits with different signal types.

摘要翻译： 公开了一种采用新颖的屏蔽技术来提高封装的高频性能的多层封装。 屏蔽通孔放置在导电通孔附近，以产生具有可控特性阻抗的双线传输线。 受控的传输线路阻抗可减少由于电感耦合引起的线路阻抗变化和接地反弹引起的信号反射。 在垂直和水平方向引入了相反的极性屏蔽技术，以减少信号之间的噪声的电容耦合，并提供抗差分电源噪声的抗扰度。 位于浮动屏蔽平面之间的信号层提供对非共模噪声耦合的抗扰度。 对于具有不同类型信号（例如CMOS和TTL和ECL型信号）的集成电路，封装产生电隔离区，以显着降低具有不同信号类型的电路之间的噪声耦合。