公开(公告)号：US08667197B2

公开(公告)日：2014-03-04

申请号：US12877871

申请日：2010-09-08

申请人： Siaw Kang Lai

发明人： Siaw Kang Lai

IPC分类号： G06F13/36

CPC分类号： G06F13/364 ,  G06F13/3625

摘要： In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种选择在仲裁期间服务的请求者的方法，以及更新与选择的请求者相关联的计数器，包括命令单元计数器和数据单元计数器，确定计数器是否符合相应阈值 值，如果是这样，授予所选择的请求者的交易，否则拒绝交易。 描述和要求保护其他实施例。

公开(公告)号：US08526601B2

公开(公告)日：2013-09-03

申请号：US10818017

申请日：2004-04-05

申请人： Atul Garg ,  Siaw-Kang Lai

发明人： Atul Garg ,  Siaw-Kang Lai

IPC分类号： H04K1/00 ,  H04L9/00 ,  G06F9/00 ,  G06F1/04

CPC分类号： H04L9/06 ,  H04L2209/12

摘要： In the present method of implementing functioning of an encryption engine, a plurality of logic blocks are provided, each for running a function. Each function is run based on three variables, each of which may have a first or second value. The function is run with the first variable value selected as having its first value, and with the second and third variables having their actual values. The function is again run with the first variable value selected as having its second value, and again with the second and third variables having their actual values. An actual value of the first variable is determined, and the output of the logic block is determined by the actual value of the first variable.

摘要翻译： 在实现加密引擎功能的现有方法中，提供多个逻辑块，每个用于运行功能。 每个函数都基于三个变量运行，每个变量可以具有第一个或第二个值。 该函数运行时，第一个变量值被选为具有其第一个值，第二个和第三个变量具有其实际值。 该函数再次运行，第一个变量值被选为具有其第二个值，再次与第二个和第三个变量具有其实际值。 确定第一个变量的实际值，逻辑块的输出由第一个变量的实际值确定。

公开(公告)号：US20050200390A1

公开(公告)日：2005-09-15

申请号：US10797836

申请日：2004-03-09

申请人： Gregory Starr ,  Wanli Chang ,  Kang Lai ,  Mian Smith ,  Richard Chang

发明人： Gregory Starr ,  Wanli Chang ,  Kang Lai ,  Mian Smith ,  Richard Chang

IPC分类号： G06F1/08 ,  G06F1/06 ,  G06F1/10 ,  H03K5/13 ,  H03K19/173 ,  H03L7/08 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H04J3/06 ,  H03L7/06

CPC分类号： H03L7/18 ,  H03L7/081 ,  H03L7/0996

摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

摘要翻译： 可编程逻辑器件包括可配置的锁相环（PLL）电路，其输出具有可编程相位和频率的多个时钟信号。 每个输出信号可编程选择用作外部时钟，内部全局时钟，内部本地时钟或其组合。 PLL电路具有可编程分频，包括可编程级联分频，以及提供高度时钟设计灵活性的可编程输出信号复用。

公开(公告)号：US20050071031A1

公开(公告)日：2005-03-31

申请号：US10672403

申请日：2003-09-26

申请人： Ta-Chin Lin ,  Yi-Feng Huang ,  Fu-Kang Lai ,  Jen-Chih Hsiao

发明人： Ta-Chin Lin ,  Yi-Feng Huang ,  Fu-Kang Lai ,  Jen-Chih Hsiao

IPC分类号： G05B19/418 ,  G06F19/00

CPC分类号： G05B19/41865 ,  G05B2219/32271 ,  G05B2219/32298 ,  G05B2219/45031 ,  Y02P90/20

摘要： A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.

公开(公告)号：US06587589B1

公开(公告)日：2003-07-01

申请号：US09514522

申请日：2000-02-28

申请人： Liang-Gee Chen ,  Po-Cheng Wu ,  Yuan-Chen Liu ,  Yeong-Kang Lai

发明人： Liang-Gee Chen ,  Po-Cheng Wu ,  Yuan-Chen Liu ,  Yeong-Kang Lai

IPC分类号： G06K946

CPC分类号： G06F17/148 ,  H04N19/42 ,  H04N19/63

摘要： An architecture for performing the two-dimensional discrete wavelet transform includes a transform module including a first stage and a second stage for decomposing an input image into four bands, and among the four bands, the band having the low frequency in both horizontal and vertical direction serves as the input image for next level decomposition operation; a multiplexer for selecting the band having the low frequency in both horizontal and vertical direction as the input image to feed into the transform module; and an optional memory module for storing the band having the lowest frequency in both horizontal and vertical direction. The polyphse decomposition technique is employed to the decimation filters of the first stage for segmenting the coefficients of the decimation filters of the first stage into an odd-numbered part and an even-numbered part, and the coefficient folding technique is employed to the decimation filters of the second stage such that every two coefficients of the decimation filters of the second stage share one set of a multiplier, an adder, and a register.

摘要翻译： 用于执行二维离散小波变换的架构包括：变换模块，包括第一级和第二级，用于将输入图像分解成四个频带，并且在四个频带中，在水平和垂直方向上具有低频的频带 作为下一级分解操作的输入图像; 用于选择具有水平和垂直方向上的低频的频带作为输入图像的多路复用器，以馈送到变换模块; 以及用于在水平和垂直方向上存储具有最低频率的频带的可选存储模块。 多重分解技术被用于第一级的抽取滤波器，用于将第一级的抽取滤波器的系数分为奇数部分和偶数部分，并且系数折叠技术被用于抽取滤波器 使得第二级的抽取滤波器的每两个系数共享一组乘法器，加法器和寄存器。

公开(公告)号：US09476750B2

公开(公告)日：2016-10-25

申请号：US14125575

申请日：2012-06-29

申请人： Gerard Andrew White ,  Ze Kang Lai

发明人： Gerard Andrew White ,  Ze Kang Lai

IPC分类号： G01F23/00 ,  A47J31/44 ,  G01F1/00 ,  G01F15/075 ,  G01F23/24 ,  G01F23/26 ,  A47J31/56

CPC分类号： G01F23/00 ,  A47J31/4457 ,  A47J31/56 ,  G01F1/007 ,  G01F15/0755 ,  G01F23/243 ,  G01F23/263

摘要： An apparatus and method of sensing fluid level in reservoir for calculating fluid flow there from. The method comprising the steps of: receiving a plurality of fluid level signals each indicative of respective fluid level state at a predetermined location within the reservoir; identifying change of a first fluid level state; recording a relative first time, with respect to fluid flow duration, at which the first fluid level state changed; and calculating fluid dispensed from the reservoir using the fluid flow duration and an average fluid flow rate associated with the respective fluid level location within the reservoir. The apparatus comprising: a plurality of fluid level probe elements located within the reservoir, each adapted to provide a respective fluid level signal; and a processor module adapted to receive receiving a plurality of fluid level signals.

摘要翻译： 一种检测储层中液位的装置和方法，用于计算流体的流量。 该方法包括以下步骤：接收多个液位信号，每个液位信号指示储存器内的预定位置处的相应液位状态; 识别第一液位状态的变化; 记录相对于第一液位状态改变的流体流动持续时间的相对第一时间; 以及使用流体流动持续时间和与储存器内的相应流体水平位置相关联的平均流体流速计算从储存器分配的流体。 所述装置包括：位于所述储存器内的多个液位探针元件，每个适于提供相应的液位信号; 以及适于接收接收多个液位信号的处理器模块。

公开(公告)号：US20060250168A1

公开(公告)日：2006-11-09

申请号：US11486565

申请日：2006-07-13

申请人： Gregory Starr ,  Wanli Chang ,  Kang Lai ,  Mian Smith ,  Richard Chang

发明人： Gregory Starr ,  Wanli Chang ,  Kang Lai ,  Mian Smith ,  Richard Chang

IPC分类号： H03L7/06

CPC分类号： H03L7/18 ,  H03L7/081 ,  H03L7/0996

摘要： A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.

公开(公告)号：US6118901A

公开(公告)日：2000-09-12

申请号：US960526

申请日：1997-10-31

申请人： Liang-Gee Chen ,  Yeong-Kang Lai ,  Yuan-Chen Liu ,  Yung-Pin Lee

发明人： Liang-Gee Chen ,  Yeong-Kang Lai ,  Yuan-Chen Liu ,  Yung-Pin Lee

IPC分类号： G06T7/20 ,  H04N7/26 ,  G06K9/36 ,  H04N5/14 ,  H04N7/12

CPC分类号： G06T7/2026 ,  H04N19/433 ,  H04N19/533 ,  G06T2207/10016

摘要： The invention discloses a 9-cell array architecture with data-rings for 3-step hierarchical search (3SHS) block-matching algorithm. With the efficient data-rings and memory organization, the regular raster-scanned data flow and comparator tree-like structure can be used to simply internal I/O controller and reduce latency. In addition, we can utilize techniques to reduce external memory accesses and interconnections. The results demonstrate that the array architecture with the data-rings is low in terms of latency, memory bandwidth and costs and a high performance solution for the 3 SHS.

摘要翻译： 本发明公开了一种具有用于三步分层搜索（3SHS）块匹配算法的数据环的9单元阵列架构。 通过高效的数据环和存储器组织，常规的光栅扫描数据流和比较树状结构可用于简单的内部I / O控制器并减少延迟。 此外，我们可以利用技术来减少外部存储器访问和互连。 结果表明，具有数据环的阵列架构在延迟，内存带宽和成本方面都很低，而3 SHS的高性能解决方案。

公开(公告)号：US20140149620A1

公开(公告)日：2014-05-29

申请号：US14169515

申请日：2014-01-31

申请人： Siaw Kang Lai

发明人： Siaw Kang Lai

IPC分类号： G06F13/364

CPC分类号： G06F13/364 ,  G06F13/3625

摘要： In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括一种选择在仲裁期间服务的请求者的方法，以及更新与选择的请求者相关联的计数器，包括命令单元计数器和数据单元计数器，确定计数器是否符合相应阈值 值，如果是这样，授予所选择的请求者的交易，否则拒绝交易。 描述和要求保护其他实施例。

公开(公告)号：US06931296B2

公开(公告)日：2005-08-16

申请号：US10672403

申请日：2003-09-26

申请人： Ta-Chin Lin ,  Yi-Feng Huang ,  Fu-Kang Lai ,  Jen-Chih Hsiao

发明人： Ta-Chin Lin ,  Yi-Feng Huang ,  Fu-Kang Lai ,  Jen-Chih Hsiao

IPC分类号： G05B19/418 ,  G06F19/00

CPC分类号： G05B19/41865 ,  G05B2219/32271 ,  G05B2219/32298 ,  G05B2219/45031 ,  Y02P90/20

摘要： A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.

摘要翻译： 一种基于两阶段事件驱动调度系统结构的半导体测试代码中灵活，全面，在线，在线，实时动态批量调度的方法和系统。 可调整的优先级公式和与PROMIS约束功能集成的调整算法可以随时在任何测试仪上提供几乎最佳的调度列表，减少错误操作。 异常规则处理特殊事件，以改善每日派遣人工工作。 本发明可以根据工程批量的测试能力自动调度工程批量，解决晶圆与封装批次之间的冲突，有效降低测试仪设置时间，更换日常手动调度单，保持高速CLIP，同时全面遵循MPS。