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公开(公告)号：US08652971B2
公开(公告)日：2014-02-18
申请号：US13411861
申请日：2012-03-05
IPC分类号： H01L21/461 , H01L23/544
CPC分类号： B81C1/00626 , B81B2203/0315 , B81C99/0065
摘要： A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.
摘要翻译： 在衬底中具有器件空腔的MEMS器件具有靠近器件腔的腔蚀刻监测器。 在衬底上形成包括电介质材料的覆盖层。 监视器刻度形成在上层上或上。 通过覆盖层蚀刻通孔，并且腔蚀刻工艺形成器件腔和监测腔。 监视器刻度位于监视器腔的侧边缘上方。 腔蚀刻监视器包括监视器刻度和监视器腔，其允许视觉测量监视器腔的横向宽度; 监视器腔的横向尺寸与装置腔的横向尺寸有关。
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公开(公告)号：US20130062720A1
公开(公告)日：2013-03-14
申请号：US13412563
申请日：2012-03-05
IPC分类号： H01L31/0203 , H01L31/18
CPC分类号： G01J5/048 , G01J5/0225 , G01J5/024 , G01J5/14 , G01J5/22
摘要： An integrated circuit chip includes a window cover over etchant holes in a dielectric layer and over a cavity in the substrate of said integrated circuit chip. The window cover extends at least 400 microns beyond the edge of the cavity. An integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edges of a cavity. A method of forming an integrated sensor chip with a sensor cover which extends at least 400 microns beyond the edge of a cavity.
摘要翻译： 集成电路芯片包括在电介质层中的蚀刻剂孔和在所述集成电路芯片的衬底中的空腔之上的窗口盖。 窗盖延伸至空腔边缘至少400微米。 具有传感器盖的集成传感器芯片，其延伸至空腔边缘至少400微米。 一种形成具有传感器盖的集成传感器芯片的方法，传感器盖延伸至空腔边缘至少400微米。
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公开(公告)号：US20120223401A1
公开(公告)日：2012-09-06
申请号：US13411861
申请日：2012-03-05
CPC分类号： B81C1/00626 , B81B2203/0315 , B81C99/0065
摘要： A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.
摘要翻译： 在衬底中具有器件空腔的MEMS器件具有靠近器件腔的腔蚀刻监测器。 在衬底上形成包括电介质材料的覆盖层。 监视器刻度形成在上层上或上。 通过覆盖层蚀刻通孔，并且腔蚀刻工艺形成器件腔和监测腔。 监视器刻度位于监视器腔的侧边缘上方。 腔蚀刻监视器包括监视器刻度和监视器腔，其允许视觉测量监视器腔的横向宽度; 监视器腔的横向尺寸与装置腔的横向尺寸有关。
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公开(公告)号：US20090184348A1
公开(公告)日：2009-07-23
申请号：US12372868
申请日：2009-02-18
IPC分类号： H01L29/78
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6653 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。
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公开(公告)号：US07510923B2
公开(公告)日：2009-03-31
申请号：US11641578
申请日：2006-12-19
IPC分类号： H01L21/338
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6653 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。
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公开(公告)号：US20120225559A1
公开(公告)日：2012-09-06
申请号：US13411871
申请日：2012-03-05
IPC分类号： H01L21/302
CPC分类号： B81C1/00047 , B81B2203/0315 , B81B2203/0353 , B81C1/00801 , B81C2201/014
摘要： A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.
摘要翻译： 一种形成具有器件空腔的MEMS器件的过程，该器件空腔将覆盖在具有可蚀刻子层的覆盖介质层堆叠覆盖在耐蚀刻下部上，包括：至少蚀刻入口孔中的上覆电介质层堆叠的可蚀刻子层以暴露 可蚀刻子层的侧面，通过保护材料覆盖可蚀刻子层的暴露表面，并随后执行腔蚀刻。 腔蚀刻掩模可以覆盖可蚀刻子层的暴露表面。 或者，可以通过回蚀工艺形成保护侧壁，以覆盖可蚀刻子层的暴露表面。 或者，可蚀刻子层的暴露的侧面可以通过各向同性蚀刻来凹陷，而不是通过回流操作来隔离，这导致访问孔蚀刻掩模的边缘落下并覆盖可蚀刻子层的暴露的侧面。
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公开(公告)号：US08642370B2
公开(公告)日：2014-02-04
申请号：US13411871
申请日：2012-03-05
IPC分类号： H01L21/00
CPC分类号： B81C1/00047 , B81B2203/0315 , B81B2203/0353 , B81C1/00801 , B81C2201/014
摘要： A process of forming a MEMS device with a device cavity underlapping an overlying dielectric layer stack having an etchable sublayer over an etch-resistant lower portion, including: etching through at least the etchable sublayer of the overlying dielectric layer stack in an access hole to expose a lateral face of the etchable sublayer, covering exposed surfaces of the etchable sublayer by protective material, and subsequently performing a cavity etch. A cavity etch mask may cover the exposed surfaces of the etchable sublayer. Alternatively, protective sidewalls may be formed by an etchback process to cover the exposed surfaces of the etchable sublayer. Alternatively, the exposed lateral face of the etchable sublayer may be recessed by an isotropic etch, than isolated by a reflow operation which causes edges of an access hole etch mask to drop and cover the exposed lateral face of the etchable sublayer.
摘要翻译： 一种形成具有器件空腔的MEMS器件的过程，该器件空腔将覆盖在具有可蚀刻子层的覆盖介质层堆叠覆盖在耐蚀刻下部上，包括：至少蚀刻入口孔中的上覆电介质层堆叠的可蚀刻子层以暴露 可蚀刻子层的侧面，通过保护材料覆盖可蚀刻子层的暴露表面，并随后执行腔蚀刻。 腔蚀刻掩模可以覆盖可蚀刻子层的暴露表面。 或者，可以通过回蚀工艺形成保护侧壁，以覆盖可蚀刻子层的暴露表面。 或者，可蚀刻子层的暴露的侧面可以通过各向同性蚀刻来凹陷，而不是通过回流操作来隔离，这导致访问孔蚀刻掩模的边缘落下并覆盖可蚀刻子层的暴露的侧面。
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公开(公告)号：US20080145991A1
公开(公告)日：2008-06-19
申请号：US11641578
申请日：2006-12-19
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/2652 , H01L29/6653 , H01L29/6656 , H01L29/7836 , Y10S257/90
摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.
摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。
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