公开(公告)号：US20080145991A1

公开(公告)日：2008-06-19

申请号：US11641578

申请日：2006-12-19

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US20090184348A1

公开(公告)日：2009-07-23

申请号：US12372868

申请日：2009-02-18

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07510923B2

公开(公告)日：2009-03-31

申请号：US11641578

申请日：2006-12-19

申请人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

发明人： Manoj Mehrotra ,  Karen Hildegard Ralston Kirmse ,  Shirin Siddiqui

IPC分类号： H01L21/338

CPC分类号： H01L29/6659 ,  H01L21/2652 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7836 ,  Y10S257/90

摘要： Slim spacers are implemented in transistor fabrication. More particularly, wide sidewall spacers are initially formed and used to guide dopants into source/drain regions in a semiconductor substrate. The wide sidewall spacers are then removed and slim sidewall spacers are formed alongside a gate stack of the transistor. The slim spacers facilitate transferring stress from an overlying pre metal dielectric (PMD) liner to a channel of the transistor, and also facilitate reducing a resistance in the transistor by allowing silicide regions to be formed closer to the channel. This mitigates yield loss by facilitating predictable or otherwise desirable behavior of the transistor.

摘要翻译： 半导体衬垫在晶体管制造中实现。 更具体地，宽侧壁间隔物最初形成并用于将掺杂剂引导到半导体衬底中的源极/漏极区。 然后去除宽的侧壁间隔物，并且在晶体管的栅极堆叠旁边形成细长的侧壁间隔物。 细长间隔件有助于将应力从上覆的预金属电介质（PMD）衬垫传递到晶体管的通道，并且还有助于通过使硅化物区域形成得更靠近沟道来减小晶体管中的电阻。 这通过促进晶体管的可预测或其它期望的行为来缓解产量损失。

公开(公告)号：US07615458B2

公开(公告)日：2009-11-10

申请号：US11764980

申请日：2007-06-19

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L21/331

CPC分类号： H01L21/2652 ,  H01L21/2255 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/823814 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。 在栅极电介质层上形成栅电极。 将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。 衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

公开(公告)号：US20090179280A1

公开(公告)日：2009-07-16

申请号：US11972417

申请日：2008-01-10

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Shaoping Tang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7833

摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed

摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。 碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。 在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。 本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。 在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。 还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

公开(公告)号：US20090065880A1

公开(公告)日：2009-03-12

申请号：US11853328

申请日：2007-09-11

申请人： Amitabh Jain ,  Manoj Mehrotra

发明人： Amitabh Jain ,  Manoj Mehrotra

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28044 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/7845

摘要： In one aspect there is provided a method of manufacturing a semiconductor device comprising forming gate electrodes over a semiconductor substrate, forming source/drains adjacent the gate electrodes, depositing a stress inducing layer over the gate electrodes. A laser anneal is conducted on at least the gate electrodes subsequent to depositing the stress inducing layer at a temperature of at least about 1100° C. for a period of time of at least about 300 microseconds, and the semiconductor device is subjected to a thermal anneal subsequent to conducting the laser anneal.

摘要翻译： 在一个方面，提供一种制造半导体器件的方法，包括在半导体衬底上形成栅电极，在栅电极附近形成源极/漏极，在栅电极上沉积应力诱导层。 在至少约1100℃的温度下沉积应力诱导层至少约300微秒的时间之后，至少在栅电极上进行激光退火，并且半导体器件经受热 在进行激光退火之后退火。

公开(公告)号：US20080277730A1

公开(公告)日：2008-11-13

申请号：US11745044

申请日：2007-05-07

申请人： Manoj Mehrotra ,  Antonio L.P Rotondaro ,  Puneet Kohli

发明人： Manoj Mehrotra ,  Antonio L.P Rotondaro ,  Puneet Kohli

IPC分类号： H01L21/44 ,  H01L29/76

CPC分类号： H01L21/76832 ,  H01L21/76825 ,  H01L21/76828 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

摘要翻译： 提出了形成半导体器件的方法。 该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。 在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底上形成层压应力层。 层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。 在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

公开(公告)号：US20080076227A1

公开(公告)日：2008-03-27

申请号：US11533795

申请日：2006-09-21

申请人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

发明人： Puneet Kohli ,  Manoj Mehrotra ,  Jin Zhao ,  Sameer Ajmera

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/2686 ,  H01L21/76224 ,  H01L21/76825 ,  H01L29/6659 ,  H01L29/7843

摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.

摘要翻译： 本发明提供一种制造半导体器件的方法。 除了其他步骤之外，用于制造半导体器件的方法包括在衬底上形成栅极结构，栅极结构具有靠近其的源极/漏极区域，并且在衬底上，衬底上或上方，在栅极上形成预金属电介质层 结构和源极/漏极区域，并且对金属前介电层进行能量束处理，所述能量束处理被配置为改变预金属介电层的应力，从而改变其下的衬底中的应力。

公开(公告)号：US20060226559A1

公开(公告)日：2006-10-12

申请号：US11103104

申请日：2005-04-11

申请人： Manoj Mehrotra ,  Hiroaki Niimi

发明人： Manoj Mehrotra ,  Hiroaki Niimi

IPC分类号： H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/76224

摘要： A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation process. An oxidation process is performed that combines with the nitrided surfaces (1312) to form a nitrogen containing liner. Subsequently, the trench region is filled with dielectric material (1316) and then planarized (1318) to remove excess dielectric fill material.

摘要翻译： 公开了一种形成包括隔离结构的半导体器件的方法（1300），并且包括在半导体本体（1308）内形成沟槽区域。 然后，通过氮化处理将沟槽区域的表面氮化（1310）。 进行与氮化表面（1312）结合以形成含氮衬里的氧化工艺。 随后，沟槽区域填充有电介质材料（1316），然后平坦化（1318）以除去多余的电介质填充材料。

公开(公告)号：US20060024909A1

公开(公告)日：2006-02-02

申请号：US10899663

申请日：2004-07-27

申请人： Manoj Mehrotra ,  Amitava Chatterjee

发明人： Manoj Mehrotra ,  Amitava Chatterjee

IPC分类号： H01L21/76

CPC分类号： H01L21/76237

摘要： A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).

摘要翻译： 提出了形成隔离结构的方法（200），其中在半导体本体（306）的隔离和有源区（305,303）上形成硬掩模层（304,308） 并且掺杂剂选择性地提供给靠近隔离区域（305）的有源区域（303）的一部分以产生阈值电压补偿区域（318）。 在创建补偿区域（318）之后，对硬掩模层（304,308）进行图案化（218）以形成图案化的硬掩模。 然后将图案化的硬掩模用于在补偿区域（318）附近的隔离区域（305）中形成（222）沟槽（323），然后用介电材料（338）填充（224）沟槽 ）。