公开(公告)号：US08724370B2

公开(公告)日：2014-05-13

申请号：US13414324

申请日：2012-03-07

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/72

摘要： A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value.

摘要翻译： 半导体存储装置包括：包括存储单元的存储单元阵列，每个存储单元具有可变电阻元件; 以及控制电路，被配置为将所述可变电阻元件所需的控制电压施加到选择的存储单元。 当多次施加控制电压时，控制电路操作以将在第一控制电压施加操作中施加的控制电压的值设置为基本上等于存储器中的所有存储器单元的电压值的分布的最小值 电池阵列需要将可变电阻元件的电阻状态从高电阻状态转移到低电阻状态。 控制电路通过将控制电压的值增加一定值来进行多个控制电压施加操作。

公开(公告)号：US08427885B2

公开(公告)日：2013-04-23

申请号：US13315967

申请日：2011-12-09

申请人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

发明人： Hideo Mukai ,  Hiroshi Maejima ,  Katsuaki Isobe

IPC分类号： G11C7/10

CPC分类号： G11C8/14 ,  G11C7/18 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/72

摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

摘要翻译： 一种非易失性半导体存储器件，包括具有以矩阵形式设置的多个MAT（单位阵列）的单元阵列，所述MAT各包括多条第一线，与第一线交叉的多条第二线，以及 存储单元连接在第一和第二线之间。 该装置还包括第一和第二驱动电路，选择连接到每个MAT的存储器单元的第一和第二线，所述存储器单元被访问，并且驱动所选择的第一和第二行来写入或读取数据。 存储单元通过连接到从MAT中选择的每个第一行形成页面。 该设备还包括以页为单位锁存写入或读取数据的数据锁存器，其中第一和第二驱动电路多次驱动第一和第二行以写入或读取单元阵列中的一页的数据。

公开(公告)号：US20130094296A1

公开(公告)日：2013-04-18

申请号：US13693449

申请日：2012-12-04

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. First select gate lines in the first block and first select gate lines in the second block are connected to the driver after they are commonly connected in one end in the second direction of the memory cell array in a relation of one to one.

公开(公告)号：US20130088918A1

公开(公告)日：2013-04-11

申请号：US13595478

申请日：2012-08-27

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C16/04 ,  G11C16/26

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： A non-volatile semiconductor memory device includes a semiconductor layer of a first conductivity type, and a plurality of wells of a second conductivity type formed on the first semiconductor layer, the wells being arranged in a first direction. A memory block is arranged in each well. A plurality of word lines are provided, each word line being commonly connected to a plurality of NAND cell units in one memory block. A plurality of bit lines extend in a first direction, the bit lines being connected to first ends of theNAND cell units present in the memory blocks. A source line is connected to second ends of the NAND cell units. A well driver performs a control of selectively providing a first voltage or a second voltage higher than the first voltage to each well.

摘要翻译： 非易失性半导体存储器件包括第一导电类型的半导体层和形成在第一半导体层上的第二导电类型的多个阱，阱沿第一方向布置。 在每个井中布置有一个记忆块。 提供多个字线，每个字线通常连接到一个存储器块中的多个NAND单元单元。 多个位线沿第一方向延伸，位线连接到存在于存储器块中的NAND单元单元的第一端。 源极线连接到NAND单元单元的第二端。 井驱动器执行选择性地向每个井提供比第一电压高的第一电压或第二电压的控制。

公开(公告)号：US20130058165A1

公开(公告)日：2013-03-07

申请号：US13424812

申请日：2012-03-20

申请人： Hiroshi MAEJIMA ,  Koji HOSONO

发明人： Hiroshi MAEJIMA ,  Koji HOSONO

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/823493 ,  H01L27/088 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

摘要： According to one embodiment, a semiconductor memory device includes a memory cells, a selection transistor, a memory string, a block, and a transfer circuit. The memory cells are stacked on a semiconductor substrate. In the memory string, the memory cells and the selection transistor are connected in series. The block includes a plurality of memory strings. In data write and read, the transfer circuit transfers a positive voltage to a select gate line associated with a selected memory string in a selected block, and a negative voltage to a select gate line associated with an unselected memory string in the selected block, and to a select gate line associated with an unselected block.

公开(公告)号：US08385104B2

公开(公告)日：2013-02-26

申请号：US13237405

申请日：2011-09-20

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C11/00

CPC分类号： G11C13/0023 ,  G11C5/025 ,  G11C8/08 ,  G11C8/10 ,  G11C8/12 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/71 ,  G11C2213/72

摘要： A semiconductor storage device includes: a memory cell array having memory cells positioned at respective intersections between a plurality of first wirings and a plurality of second wirings, each of the memory cells having a rectifier element and a variable resistance element connected in series; and a control circuit selectively driving the first and second wirings. The plurality of first wirings that are specified and selectively driven at the same time by one of a plurality of address signals are separately arranged with other first wirings interposed therebetween within the memory cell array when a certain potential difference is applied to a selected memory cell positioned at an intersection between the first and second wirings by the control circuit.

公开(公告)号：US08379449B2

公开(公告)日：2013-02-19

申请号：US13336122

申请日：2011-12-23

申请人： Hiroshi Maejima

发明人： Hiroshi Maejima

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/063 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/3422

摘要： A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

摘要翻译： 根据本发明的示例的三维堆叠的非易失性半导体存储器包括由第一和第二块组成的存储单元阵列。 第一块具有第一单元单元，其包括要编程的存储器单元和不包括要编程的存储单元的第二单元单元，并且通过将程序电位或转移电位施加到 在第一和第二单元单元中的存储器单元的通道的初始电位被设置为正电位之后的第一块。 在编程中，程序电位和转移电位不适用于第二个程序段中的字线。

公开(公告)号：US08345466B2

公开(公告)日：2013-01-01

申请号：US12849407

申请日：2010-08-03

申请人： Hiroshi Maejima ,  Koji Hosono

发明人： Hiroshi Maejima ,  Koji Hosono

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/56 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array including: a plurality of first lines; a plurality of second lines intersecting the first lines; and a plurality of memory cells each including a variable resistance element disposed at the intersection of the first and second lines and configured to store an electrically rewritable resistance value as data in a nonvolatile manner, and a control unit configured to detect an amount of a current flowing through the first line when a memory cell is accessed, and adjust the voltage of the first or second line based on the amount of the current.

摘要翻译： 根据实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一线; 与第一线相交的多个第二线; 以及多个存储单元，每个存储单元包括设置在第一和第二行的交叉点处的可变电阻元件，并且被配置为以非易失性方式存储作为数据的电可重写电阻值;以及控制单元，被配置为检测电流量 当访问存储器单元时流过第一行，并且基于电流量来调整第一行或第二行的电压。

公开(公告)号：US20120163060A1

公开(公告)日：2012-06-28

申请号：US13412159

申请日：2012-03-05

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C5/02

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/145

摘要： A semiconductor memory device comprises a semiconductor substrate; a plurality of memory cell arrays stacked on the semiconductor substrate, each memory cell array including a plurality of first lines paralleled with each other, a plurality of second lines paralleled with each other and formed crossing the first lines, and a plurality of memory cells arranged at intersections of the first lines and the second lines, each memory cell having one end connected to the first line and the other end connected to the second line; a first control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the first line to select and drive the first line; and a second control circuit provided on the semiconductor substrate immediately beneath the memory cell arrays and having one end connected to the second line to select and drive the second line.

摘要翻译： 半导体存储器件包括半导体衬底; 堆叠在半导体衬底上的多个存储单元阵列，每个存储单元阵列包括彼此平行的多条第一线，彼此并联并形成为与第一线交叉形成的多条第二线，以及多条存储单元， 在第一行和第二行的交叉点处，每个存储单元的一端连接到第一行，另一端连接到第二行; 第一控制电路，设置在存储单元阵列正下方的半导体衬底上，并且一端连接到第一行以选择和驱动第一行; 以及第二控制电路，设置在存储单元阵列正下方的半导体基板上，并且一端连接到第二线以选择和驱动第二线。

公开(公告)号：US20120140549A1

公开(公告)日：2012-06-07

申请号：US13398281

申请日：2012-02-16

申请人： Hiroshi MAEJIMA

发明人： Hiroshi MAEJIMA

IPC分类号： G11C11/00

CPC分类号： G11C7/04 ,  G11C5/02 ,  G11C5/063 ,  G11C5/147 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor memory device comprises a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，其包括布置在第一和第二线的交点处的第一和第二相交线和电可擦除可编程存储器单元，每个存储单元包含可变电阻器，用于将其电阻非常地存储为数据， 用于切换可变电阻器的第一非欧姆元件; 以及钳位电压发生器电路，用于产生对存储单元的访问所需的钳位电压并施加到第一和第二线路。 钳位电压发生器电路具有补偿第一非欧姆元件的温度特性的温度补偿功能。