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    Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device
    2.
    发明授权
    Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device 有权
    在可变电阻非易失性存储元件上形成的形成方法以及可变电阻非易失性存储器件

    公开(公告)号：US08848421B2

    公开(公告)日：2014-09-30

    申请号：US13634161

    申请日：2011-03-28

    申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama

    发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama

    IPC分类号： G11C11/00 ,  H01L45/00 ,  H01L27/10 ,  G11C13/00 ,  H01L27/24

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    摘要： A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

    摘要翻译： 一种可变电阻非易失性存储元件的形成方法，其能够降低形成电压并防止取决于可变电阻元件的形成电压的变化。 该形成方法用于初始化可变电阻元件，包括确定在1T1R存储单元中流动的电流是否大于参考电流的步骤（S24）; 当确定电流不大于参考电流时，施加具有脉冲宽度（Tp（n））的形成正电压脉冲的步骤（S22）逐渐增加; 以及施加脉冲宽度Tn等于或短于脉冲宽度Tp（n）的负电压脉冲的步骤（S23）。 重复确定步骤（S24），应用步骤（S22）和应用步骤（S23），直到形成成功。

    Variable resistance nonvolatile memory device
    3.
    发明授权
    Variable resistance nonvolatile memory device 有权
    可变电阻非易失性存储器件

    公开(公告)号：US08687409B2

    公开(公告)日：2014-04-01

    申请号：US13639120

    申请日：2012-05-30

    申请人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Ryotaro Azuma ,  Ken Kawai

    发明人： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Ryotaro Azuma ,  Ken Kawai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/72

    摘要： A variable resistance nonvolatile memory device including memory cells provided at cross-points of first signal lines and second signal lines, each memory cell including a variable resistance element and a current steering element connected to the variable resistance element in series, the variable resistance nonvolatile memory device including a write circuit, a row selection circuit, and a column selection circuit, wherein the write circuit: sequentially selects blocks in an order starting from a block farthest from at least one of the row selection circuit and the column selection circuit and finishing with a block closest to the at least one of the row selection circuit and the column selection circuit; and performs, for each of the selected blocks, initial breakdown on each memory cell included in the selected block.

    摘要翻译： 一种可变电阻非易失性存储器件，包括设置在第一信号线和第二信号线的交叉点处的存储单元，每个存储单元包括可变电阻元件和连接到可变电阻元件串联的电流操舵元件，可变电阻非易失性存储器 包括写入电路，行选择电路和列选择电路的装置，其中写入电路：从与行选择电路和列选择电路中的至少一个最远的块开始的顺序顺序地选择块，并且以 最靠近行选择电路和列选择电路中的至少一个的块; 并且对于每个所选择的块，对包括在所选择的块中的每个存储器单元执行初始故障。

    CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY
    4.
    发明申请
    CROSS POINT VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE AND METHOD OF READING THEREBY 有权
    交叉点可变电阻非易失性存储器件及其读取方法

    公开(公告)号：US20130077384A1

    公开(公告)日：2013-03-28

    申请号：US13636169

    申请日：2012-04-27

    申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

    发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

    IPC分类号： G11C11/21

    CPC分类号： G11C11/21 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/15 ,  G11C2213/71

    摘要： A cross point variable resistance nonvolatile memory device including: a cross point memory cell array having memory cells each of which is placed at a different one of cross points of bit lines and word lines; a word line decoder circuit that selects at least one of the memory cells from the memory cell array; a read circuit that reads data from the selected memory cell; an unselected word line current source that supplies a first constant current; and a control circuit that controls the reading of the data from the selected memory cell, wherein the control circuit controls the word line decoder circuit, the read circuit, and the unselected word line current source so that when the read circuit reads data, the first constant current is supplied to an unselected word line.

    摘要翻译： 一种交叉点可变电阻非易失性存储器件，包括：具有存储单元的交叉点存储单元阵列，每个存储单元位于位线和字线的交叉点的不同位置; 字线解码器电路，从存储单元阵列中选择至少一个存储单元; 从所选择的存储单元读取数据的读取电路; 提供第一恒定电流的未选字线电流源; 以及控制电路，其控制来自所选择的存储单元的数据的读取，其中所述控制电路控制所述字线解码器电路，所述读取电路和所述未选字线电流源，使得当所述读取电路读取数据时，所述第一 恒定电流被提供给未选择的字线。

    FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE
    5.
    发明申请
    FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
    形成可变电阻非易失性存储器元件和可变电阻非易失性存储器件的形成方法

    公开(公告)号：US20130044534A1

    公开(公告)日：2013-02-21

    申请号：US13634161

    申请日：2011-03-28

    申请人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama

    发明人： Ken Kawai ,  Kazuhiko Shimakawa ,  Koji Katayama

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

    摘要： A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

    摘要翻译： 一种可变电阻非易失性存储元件的形成方法，其能够降低形成电压并防止取决于可变电阻元件的形成电压的变化。 该形成方法用于初始化可变电阻元件，包括确定在1T1R存储单元中流动的电流是否大于参考电流的步骤（S24）; 当确定电流不大于参考电流时，施加具有脉冲宽度（Tp（n））的形成正电压脉冲的步骤（S22）逐渐增加; 以及施加脉冲宽度Tn等于或短于脉冲宽度Tp（n）的负电压脉冲的步骤（S23）。 重复确定步骤（S24），应用步骤（S22）和应用步骤（S23），直到形成成功。

    Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device
    6.
    发明授权
    Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device 有权
    非易失性可变电阻存储元件写入方法和非易失性可变电阻存储器件

    公开(公告)号：US08305795B2

    公开(公告)日：2012-11-06

    申请号：US12999019

    申请日：2010-04-27

    申请人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

    发明人： Ryotaro Azuma ,  Kazuhiko Shimakawa ,  Shunsaku Muraoka ,  Ken Kawai

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/56 ,  G11C2213/79

    摘要： To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing data to a variable resistance element (10a) that reversibly changes between a high resistance state and a low resistance state according to a polarity of an applied voltage, as a voltage applied to an upper electrode (11) with respect to a lower electrode (14t): a positive voltage is applied in a high resistance writing step (405) to set the variable resistance element (10a) to a high resistance state (401); a negative voltage is applied in a low resistance writing step (406, 408) to set the variable resistance element (10a) to a low resistance state (403, 402); and a positive voltage is applied in a low resistance stabilization writing step (404) after the negative voltage is applied in the low resistance writing step (408), thereby setting the variable resistance element (10a) through the low resistance state to the high resistance state (401).

    摘要翻译： 为了提供可变电阻元件写入方法，即使当可变电阻元件具有成为半LR状态的可能性时，通过将可变电阻元件校正为正常的低电阻状态来确保最大电阻变化窗口。 在根据施加电压的极性将数据写入到可变电阻元件（10a）的方法中，可变电阻元件（10a）根据施加电压的极性在高电阻状态和低电阻状态之间可逆地变化，作为施加到上电极（11）的电压相对于 下电极（14t）：在高电阻写入步骤（405）中施加正电压以将可变电阻元件（10a）设置为高电阻状态（401）; 在低电阻写入步骤（406,408）中施加负电压以将可变电阻元件（10a）设置为低电阻状态（403,402）; 并且在低电阻写入步骤（408）中施加负电压之后，在低电阻稳定写入步骤（404）中施加正电压，从而将可变电阻元件（10a）设置为低电阻状态为高电阻 州（401）。

    Nonvolatile memory apparatus and nonvolatile data storage medium
    7.
    发明授权
    Nonvolatile memory apparatus and nonvolatile data storage medium 有权
    非易失性存储装置和非易失性数据存储介质

    公开(公告)号：US08094482B2

    公开(公告)日：2012-01-10

    申请号：US12529466

    申请日：2008-10-28

    申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

    发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

    IPC分类号： G11C11/00

    CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

    摘要： A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.

    摘要翻译： 本发明的非易失性存储装置和非易失性数据存储介质，包括各自根据施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路，其中施加第一电脉冲到 将非易失性存储元件的电阻值从第一电阻值切换到与第一电脉冲极性相反的第二电阻值和第二电脉冲的非易失性存储元件施加到非易失性存储元件，以将电阻 非易失性存储元件的值从第二电阻值到第一电阻值。

    VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE
    9.
    发明申请
    VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE 有权
    可变电阻非易失性存储器件

    公开(公告)号：US20110122680A1

    公开(公告)日：2011-05-26

    申请号：US13054312

    申请日：2010-04-14

    申请人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

    发明人： Yuuichirou Ikeda ,  Kazuhiko Shimakawa ,  Yoshihiko Kanzawa ,  Shunsaku Muraoka ,  Ryotaro Azuma

    IPC分类号： G11C11/21

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/12 ,  G11C2213/15 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/24

    摘要： A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.

    摘要翻译： 一种非易失性电阻可变存储器件（100）包括存储单元（M11，M12 ...），每个存储单元包括可变电阻元件（R11，R12 ...），该可变电阻元件（R11，R12 ...） 第一电极和第二电极，以及包括放置在第三电极和第四电极之间并与第三电极和第四电极接触的电流导向层的电流导向元件（D11，D12 ...）串联连接，并且驱动该装置 通过第一LR驱动电路（105a1）经由限流电路（105b），以在器件被第二HR驱动电路（105a2）驱动时降低可变电阻元件的电阻，以增加可变电阻元件的电阻，从而使用 电流限制电路（105b），用于使可变电阻元件的电阻降低的电流低于用于增加可变电阻元件的电阻的电流。