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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07466619B2

    公开(公告)日：2008-12-16

    申请号：US11760959

    申请日：2007-06-11

    申请人： Kenji Mae

    发明人： Kenji Mae

    IPC分类号： G11C8/00

    CPC分类号： G11C8/12 ,  G11C7/18 ,  G11C11/4087 ,  G11C11/4097 ,  G11C29/783

    摘要： A semiconductor memory device includes a plurality of banks #0 to #3, a predecoder that generates a predecode signal, first latch circuits, each of which is assigned to the banks, that hold a first portion of the predecode signal, a main decoder that is assigned in common to the two banks, and receives a second portion of the predecode signal and outputs of the first latch circuits. The main decoder includes latch circuits that hold by each bank a decoded signal obtained by decoding the second portion of the predecode signal. In the present invention, an address through predecoder is used to latch a predecode signal, and hence it becomes possible to share one portion of the predecode signal between the banks.

    摘要翻译： 半导体存储器件包括：多个存储体＃0至＃3，产生预解码信号的预解码器，分配给存储器的每个分配给存储体的第一锁存电路，其存储预解码信号的第一部分;主解码器， 被分配给两个组，并且接收第二部分的预解码信号和第一锁存电路的输出。 主解码器包括由每个存储体通过解码预解码信号的第二部分而获得的解码信号的锁存电路。 在本发明中，地址通过预解码器用于锁存预解码信号，因此可以在两个存储体之间共享一部分预解码信号。

    Boosted potential generation circuit and control method
    2.
    发明授权
    Boosted potential generation circuit and control method 有权
    增强潜力发电电路及控制方法

    公开(公告)号：US06954386B2

    公开(公告)日：2005-10-11

    申请号：US10372000

    申请日：2003-02-20

    申请人： Seiji Narui ,  Kenji Mae ,  Makoto Morino ,  Shuichi Kubouchi

    发明人： Seiji Narui ,  Kenji Mae ,  Makoto Morino ,  Shuichi Kubouchi

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H02M3/07 ,  G11C7/00

    CPC分类号： G11C11/4074 ,  G11C5/145

    摘要： A boosted potential generation circuit enables a high-speed operation and even miniaturization in a semiconductor memory even if external power supply voltage is reduced in the semiconductor memory. In the boosted potential generation circuit provided with a capacitor MOS transistor and a transfer MOS transistor and used for a DRAM including memory cells, a gate insulating film of the capacitor MOS transistor is thinner than that of the MOS transistor constituting the memory cell to realize a boosted potential generation circuit which has a small area and a large capacity. In this case, preferably, the gate insulating film of the transfer MOS transistor has a thickness which is not greater than that of the gate insulating film of the capacitor MOS transistor.

    摘要翻译： 即使在半导体存储器中外部电源电压降低，升压电位产生电路也可实现半导体存储器中的高速操作甚至小型化。 在设置有电容器MOS晶体管和转移MOS晶体管并且用于包括存储单元的DRAM的升压电位产生电路中，电容器MOS晶体管的栅绝缘膜比构成存储单元的MOS晶体管的栅极绝缘膜薄，以实现 具有小面积和大容量的增强型电位发生电路。 在这种情况下，优选地，转移MOS晶体管的栅极绝缘膜的厚度不大于电容器MOS晶体管的栅极绝缘膜的厚度。

    Semiconductor memory device and control method thereof
    3.
    发明授权
    Semiconductor memory device and control method thereof 有权
    半导体存储器件及其控制方法

    公开(公告)号：US08036057B2

    公开(公告)日：2011-10-11

    申请号：US12385959

    申请日：2009-04-24

    申请人： Kenji Mae

    发明人： Kenji Mae

    IPC分类号： G11C7/00

    CPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A semiconductor memory device (and control method therefor) includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells arranged at intersections of the word lines and the bit lines, a word driver that selects any one of the word lines, a plurality of sense amplifiers connectable to any of the bit lines, a sense-amplifier starting circuit that sequentially starts the sense amplifiers in response to a request of consecutive read operations to the memory cells connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver, and an address determining circuit that temporarily stops an operation of the sense-amplifier starting circuit in response to a request of consecutive read operations to a same memory cell connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver.

    摘要翻译： 一种半导体存储器件（及其控制方法）包括多个字线，多个位线，布置在字线和位线的交点处的多个存储单元，选择字中的任一个的字驱动器 线路，可连接到任何位线的多个读出放大器，读出放大器启动电路，响应于对连接到预定字线的存储器单元的连续读取操作的请求，以一种状态顺序地启动读出放大器 由字驱动器选择预定字线，以及地址确定电路，其响应于连续读操作的请求而临时停止读出放大器启动电路的操作到连接到预定字线的相同存储单元， 在字驱动器中选择了预定字线的状态。

    Semiconductor memory device
    5.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号：US20080298154A1

    公开(公告)日：2008-12-04

    申请号：US12153994

    申请日：2008-05-28

    申请人： Kenji Mae

    发明人： Kenji Mae

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C29/783 ,  G11C2211/4065

    摘要： A semiconductor memory device includes: a plurality of banks each of which includes a plurality of mats each having normal word lines and redundant word lines; a first refresh generating circuit that generates a first refresh start signal for performing a first refresh operation in response to input of a refresh command; and a second refresh generating circuit that generates a second refresh start signal for performing a second refresh operation in response to a refresh operation end signal indicating that the first refresh operation ends.

    摘要翻译： 半导体存储器件包括：多个存储体，每个存储体包括多个具有正常字线和冗余字线的垫; 第一刷新生成电路，其响应于刷新命令的输入而生成用于执行第一刷新操作的第一刷新开始信号; 以及第二刷新生成电路，其响应于指示第一刷新操作结束的刷新操作结束信号，生成用于执行第二刷新操作的第二刷新开始信号。

    Semiconductor memory device having DRAM-compatible addressing mode and data processing system including same
    7.
    发明授权
    Semiconductor memory device having DRAM-compatible addressing mode and data processing system including same 有权
    具有DRAM兼容寻址模式的半导体存储器件和包括它的数据处理系统

    公开(公告)号：US08072794B2

    公开(公告)日：2011-12-06

    申请号：US12572699

    申请日：2009-10-02

    申请人： Satoshi Katagiri ,  Kenji Mae

    发明人： Satoshi Katagiri ,  Kenji Mae

    IPC分类号： G11C11/00

    CPC分类号： G11C8/12 ,  G11C7/08 ,  G11C8/18

    摘要： In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area.

    摘要翻译： 与活动命令同步，同时接收行地址和列地址，并且与读命令或写命令同步地接收页地址。 字驱动程序根据行地址选择字线，列开关根据列地址选择位线。 页面地址解码器基于页面地址选择与每个页面相对应的读/写放大器中的任何一个。 利用这种配置，可以满足诸如访问周期的DRAM的规范，而不需要为每个位线布置放大器，因此可以在减小芯片面积的同时确保与DRAM的兼容性。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130058154A1

    公开(公告)日：2013-03-07

    申请号：US13602544

    申请日：2012-09-04

    申请人： Satoshi KATAGIRI ,  Kenji MAE

    发明人： Satoshi KATAGIRI ,  Kenji MAE

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0002 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50008 ,  G11C2029/5004

    摘要： A semiconductor device includes a plurality of first memory cells, at least one of second memory cells, and a control circuit. The plurality of first memory cells are accessed during normal operation, wherein the first memory cell includes a first variable resistance element. The second memory cell is not accessed during the normal operation but accessed at a time of test operation. The second memory cell includes a second variable resistance element practically identical to the first variable resistance element. The control circuit performs forming on the second memory cell at the time of the test operation.

    摘要翻译： 半导体器件包括多个第一存储单元，第二存储单元和控制电路中的至少一个。 多个第一存储单元在正常操作期间被访问，其中第一存储单元包括第一可变电阻元件。 第二个存储单元在正常操作期间不被访问，但在测试操作时被访问。 第二存储单元包括实质上与第一可变电阻元件相同的第二可变电阻元件。 控制电路在测试操作时在第二存储单元上进行形成。

    Semiconductor memory device and control method thereof
    10.
    发明申请
    Semiconductor memory device and control method thereof 有权
    半导体存储器件及其控制方法

    公开(公告)号：US20090268514A1

    公开(公告)日：2009-10-29

    申请号：US12385959

    申请日：2009-04-24

    申请人： Kenji Mae

    发明人： Kenji Mae

    IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/00 ,  G11C11/416

    CPC分类号： G11C8/08 ,  G11C7/06 ,  G11C7/22 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054 ,  G11C2213/79

    摘要： A semiconductor memory device includes: a plurality of word lines; a plurality of bit lines; plurality of memory cells arranged at intersections of the word lines and the bit lines; a word driver that selects any one of the word lines; a plurality of sense amplifiers connectable to any of the bit lines; a sense-amplifier starting circuit that sequentially starts the sense amplifiers in response to a request of consecutive read operations to the memory cells connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver; and an address determining circuit that temporarily stops an operation of the sense-amplifier starting circuit in response to a request of consecutive read operations to a same memory cell connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver.

    摘要翻译： 半导体存储器件包括：多个字线; 多个位线; 布置在字线和位线的交点处的多个存储单元; 选择任何一个字线的字驱动器; 多个读出放大器，可连接到任一位线; 感测放大器启动电路，在由字驱动器选择了预定字线的状态下，响应于对连接到预定字线的存储单元的连续读取操作的请求，顺序启动读出放大器; 以及地址确定电路，其在由所述预定字线选择了所述预定字线的状态下，响应于对连接到预定字线的相同存储单元的连续读取操作的请求而临时停止所述读出放大器启动电路的操作 字驱动