公开(公告)号：US5943599A

公开(公告)日：1999-08-24

申请号：US920133

申请日：1997-08-27

申请人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

发明人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/3145 ,  Y10S438/958

摘要： A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

摘要翻译： 金属层（24）形成在隔离层（22）上以用作互连。 随后，沿着金属层（24）的表面可选地形成薄衬层（26），用作缓冲层。 未掺杂的硅酸盐玻璃（USG）层（28）沉积在衬层（26）上。 USG层（28）使用臭氧和原硅酸四乙酯（TEOS）作为源，在约380至420℃的温度下形成。氧气用作臭氧的载体。 氧气的流量约为4000〜6000sccm。 氦气用作TEOS的载体。 氦气的流量约为3000〜5000sccm。 使用等离子体增强化学气相沉积（PECVD）在USG层（28）上沉积氮化硅层（30）。 氮化硅层（30）用作主钝化层。 氮化硅层（30）的厚度约为3000至7000埃。

公开(公告)号：US5851603A

公开(公告)日：1998-12-22

申请号：US891910

申请日：1997-07-14

申请人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

发明人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B05D3/06

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

摘要： A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

摘要翻译： 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。

公开(公告)号：US6107171A

公开(公告)日：2000-08-22

申请号：US113974

申请日：1998-07-09

申请人： Kwong-Jr Tsai

发明人： Kwong-Jr Tsai

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/3205

CPC分类号： H01L21/28061 ,  H01L21/28114 ,  H01L29/4941

摘要： The present invention discloses a method to manufacture metal gate of integrated circuits. A gate oxide layer is formed on a substrate and a polysilicon layer is then deposited on the gate oxide layer. Afterwards, a barrier layer is formed on the polysilicon layer and a metal layer is deposited on the barrier layer. An etching process is performed to etch the metal layer and the barrier layer, and a metal gate is defined. Then, silicon nitride liners are formed on the sidewalls of the metal gate. Finally, silicon nitride spacers are formed on the silicon nitride liners and on the sidewalls of the polysilicon gate to serve as an insulating layer.

摘要翻译： 本发明公开了一种制造集成电路金属栅极的方法。 在衬底上形成栅极氧化层，然后在栅极氧化物层上沉积多晶硅层。 之后，在多晶硅层上形成阻挡层，在阻挡层上沉积金属层。 执行蚀刻工艺以蚀刻金属层和阻挡层，并且限定金属栅极。 然后，在金属栅极的侧壁上形成氮化硅衬垫。 最后，在氮化硅衬垫和多晶硅栅极的侧壁上形成氮化硅衬垫以用作绝缘层。

公开(公告)号：US6017614A

公开(公告)日：2000-01-25

申请号：US157510

申请日：1998-09-21

申请人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

发明人： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B32B3/00

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

摘要： A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

摘要翻译： 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。

公开(公告)号：US06277719B1

公开(公告)日：2001-08-21

申请号：US09439364

申请日：1999-11-15

申请人： Jin-Dong Chern ,  Kwong-Jr Tsai ,  Ing-Ruey Liaw ,  Randy C. H. Chang

发明人： Jin-Dong Chern ,  Kwong-Jr Tsai ,  Ing-Ruey Liaw ,  Randy C. H. Chang

IPC分类号： H01L213205

CPC分类号： H01L21/28052 ,  H01L21/28061 ,  H01L21/324 ,  H01L29/4941

摘要： A method for forming a low resistance metal/polysilicon gate for use in CMOS devices comprising: (1) a novel anneal step prior to formation of a diffusion barrier layer and (2) a novel diffusion barrier layer composed of titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon. A first insulating layer is formed over a silicon substrate, and a polysilicon layer is formed over the first insulating layer. In a key step, the polysilicon layer is annealed to prevent peeling of the subsequently formed diffusion barrier layer. A diffusion barrier layer comprising titanium nitride deposited over titanium silicide or titanium nitride deposited directly on the polysilicon is formed over the polysilicon layer. A tungsten layer is formed over the diffusion barrier layer, and a capping layer comprising a silicon nitride layer over an oxide layer can be formed over the tungsten layer. The capping layer, the tungsten layer, the diffusion barrier layer, and the first insulating layer are patterned, thereby defining a gate structure.

摘要翻译： 一种用于形成用于CMOS器件的低电阻金属/多晶硅栅极的方法，包括：（1）在形成扩散阻挡层之前的新型退火步骤和（2）由沉积在硅化钛上的氮化钛组成的新型扩散阻挡层 或直接沉积在多晶硅上的氮化钛。 在硅衬底上形成第一绝缘层，并且在第一绝缘层上形成多晶硅层。 在关键步骤中，多晶硅层退火以防止随后形成的扩散阻挡层的剥离。 在多晶硅层上形成包含沉积在直接沉积在多晶硅上的硅化钛或氮化钛上的氮化钛的扩散阻挡层。 在扩散阻挡层上形成钨层，并且可以在钨层之上形成包含氧化物层上方的氮化硅层的覆盖层。 对覆盖层，钨层，扩散阻挡层和第一绝缘层进行图案化，由此限定栅极结构。

公开(公告)号：US5962344A

公开(公告)日：1999-10-05

申请号：US999229

申请日：1997-12-29

申请人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

发明人： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

IPC分类号： H01L21/318 ,  H01L21/441

CPC分类号： H01L21/3185

摘要： A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.

摘要翻译： 实现了用于在ULSI电路上的金属互连上形成改进的PECVD氮化硅膜钝化层的等离子体处理方法。 该过程在单个PECVD反应器中进行。 在金属线上沉积薄氧化硅应力释放层之后，沉积等离子体增强的CVD氮化硅层，随后在氮化硅层上进行等离子体处理步骤。 使用足够薄的氮化硅层在下一个光刻胶工艺步骤消除光致抗蚀剂捕获，否则将被捕获在通常在紧密间隔的金属线之间的氮化硅钝化层中形成的空隙（键槽）中，并且可能导致腐蚀 金属。 然后，使用He，Ar中的等离子体处理或两者的混合物来使氮化硅层致密化并且基本上减少否则将引起层间金属短路的针孔。