公开(公告)号：US5943599A

公开(公告)日：1999-08-24

申请号：US920133

申请日：1997-08-27

申请人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

发明人： Liang-Gi Yao ,  Yeur-Luen Tu ,  Sen-Huan Huang ,  Kwong-Jr Tsai ,  Meng-Jaw Cherng

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/4763

CPC分类号： H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/3145 ,  Y10S438/958

摘要： A metal layer (24) is formed on an isolation layer (22) to act as interconnections. Subsequently, a thin liner layer (26) is optionally formed along the surface of the metal layer (24) to serve as a buffer layer. An undoped silicate glass (USG) layer (28) is deposited on the liner layer (26). The USG layer (28) is formed using ozone and tetraethylorthosilicate (TEOS) as a source at a temperature of approximately 380 to 420.degree. C. Oxygen gas is used as a carrier for the ozone. The flow rate of the oxygen gas is approximately 4000 to 6000 sccm. Helium gas is used as a carrier for the TEOS. The flow rate of the helium is approximately 3000 to 5000 sccm. A silicon nitride layer (30) is deposited on the USG layer (28) using plasma enhanced chemical vapor deposition (PECVD). The silicon nitride layer (30) serves as a main passivation layer. The thickness of the silicon nitride layer (30) is approximately 3000 to 7000 angstroms.

摘要翻译： 金属层（24）形成在隔离层（22）上以用作互连。 随后，沿着金属层（24）的表面可选地形成薄衬层（26），用作缓冲层。 未掺杂的硅酸盐玻璃（USG）层（28）沉积在衬层（26）上。 USG层（28）使用臭氧和原硅酸四乙酯（TEOS）作为源，在约380至420℃的温度下形成。氧气用作臭氧的载体。 氧气的流量约为4000〜6000sccm。 氦气用作TEOS的载体。 氦气的流量约为3000〜5000sccm。 使用等离子体增强化学气相沉积（PECVD）在USG层（28）上沉积氮化硅层（30）。 氮化硅层（30）用作主钝化层。 氮化硅层（30）的厚度约为3000至7000埃。

公开(公告)号：US6022776A

公开(公告)日：2000-02-08

申请号：US287998

申请日：1999-04-07

申请人： Wan Yih Lien ,  Kung Linliu ,  Meng-Jaw Cherng

发明人： Wan Yih Lien ,  Kung Linliu ,  Meng-Jaw Cherng

IPC分类号： H01L21/8242

CPC分类号： H01L27/10844 ,  H01L27/10852

摘要： A method for forming a DRAM cell of a DRAM circuit is disclosed. The DRAM circuit includes a periphery region and a cell region. The DRAM cell is in the cell region and comprises an access transistor and a capacitor. The access transistor has a gate, a source, and a drain. The periphery region includes a plurality of gates. The method comprises the deposition of a silicon oxynitride layer over the gates, the silicon oxynitride layer acting as a bottom anti-reflection coating. That portion of the silicon oxynitride layer that lies over the DRAM cell is removed. A landing pad is formed over the source of the access transistor and a bitline pad is formed over the drain of the transistor. Next, a first oxide layer is formed over the landing pad and the bitline pad. A capacitor is formed over the landing pad and a second oxide layer is formed over the capacitor. Finally, metal contacts are formed to at least one of the gates in the periphery region using the silicon oxynitride layer as a buffer layer to prevent substrate loss or overetching.

摘要翻译： 公开了一种用于形成DRAM电路的DRAM单元的方法。 DRAM电路包括外围区域和单元区域。 DRAM单元位于单元区域中，并且包括存取晶体管和电容器。 存取晶体管具有栅极，源极和漏极。 周边区域包括多个门。 该方法包括在栅极上沉积氧氮化硅层，氧氮化硅层用作底部防反射涂层。 位于DRAM单元上方的氧氮化硅层的部分被去除。 在存取晶体管的源极上形成着键盘，并且在晶体管的漏极上方形成位线焊盘。 接下来，在着陆焊盘和位线焊盘上形成第一氧化物层。 在着陆焊盘上形成电容器，并且在电容器上形成第二氧化物层。 最后，使用氮氧化硅层作为缓冲层，在外围区域的至少一个栅极上形成金属接触，以防止基板损失或过蚀刻。

公开(公告)号：US6150247A

公开(公告)日：2000-11-21

申请号：US590548

申请日：1996-03-19

申请人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

发明人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

IPC分类号： H01L21/3205

CPC分类号： H01L21/32053 ,  H01L21/32055

摘要： A method for making interlevel contacts having low contact resistance (R.sub.c) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi.sub.2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide interconnecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (R.sub.c). This low R.sub.c is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconnecting polycide layer.

摘要翻译： 描述了在图案化的多晶硅化物层之间制造具有低接触电阻（Rc）的层间接触的方法。 该方法和所得的接触结构包括沉积和电导掺杂具有第一硅化钨（WSi2）层的第一多晶硅层。 将第一多晶硅/硅化物（第一多晶硅）层图案化以形成第一多晶硅互连导电层。 在图案化的第一多晶硅化物层上沉积绝缘层，并且将绝缘层中的各向异性等离子体蚀刻接触开口到下面的多晶硅化物层。 蚀刻继续完全去除接触开口中的第一硅化物层，并蚀刻入第一多晶硅层。 在短暂的氢氟酸（HF）蚀刻之后，沉积第二掺杂多晶硅层并图案化以在接触开口上形成第二导电互连层。 在触点中形成的第二多晶硅到第一多晶硅界面导致一致的低接触电阻（Rc）。 这种低Rc在现有技术中难以实现，其中第二级冶金接触第一级互连多晶硅化物层的第一硅化钨。

公开(公告)号：US5543345A

公开(公告)日：1996-08-06

申请号：US579167

申请日：1995-12-27

申请人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

发明人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/92

摘要： A method is provided for fabricating a single crown electrode for a capacitor for semiconductor memory devices. A conductive layer is formed over a multi-layer gate and insulation structure. The conductive layer includes a portion extending through a contact hole to thereby electrically connect the conductive layer with an active region of a transistor formed in the substrate Next, a novel groove is etched in the conductive layer between adjacent memory cells. Sidewall spacers are formed on the groove. The conductive layer is anisotropically etched using the spacers as an etching mask, thereby forming a plurality of electrodes having upright portions. The etching exposes the first insulation layer in the area under the grooves, but leaves a thickness of the base conductive layer to form the bottom of the electrode. The spacers then are removed and a conformal dielectric layer is formed over the surface. Lastly, a top plate electrode is formed over the conformal dielectric layer.

摘要翻译： 提供了一种用于制造用于半导体存储器件的电容器的单冠状电极的方法。 在多层栅极和绝缘结构上形成导电层。 导电层包括延伸穿过接触孔的部分，从而将导电层与形成在衬底中的晶体管的有源区电连接。接下来，在相邻存储单元之间的导电层中蚀刻新的沟槽。 在槽上形成侧壁间隔物。 使用间隔物作为蚀刻掩模对导电层进行各向异性蚀刻，从而形成具有直立部分的多个电极。 蚀刻在凹槽下方的区域中暴露第一绝缘层，但留下基底导电层的厚度以形成电极的底部。 然后去除间隔物，并且在表面上形成共形介电层。 最后，在保形电介质层上形成顶板电极。

公开(公告)号：US06211091B1

公开(公告)日：2001-04-03

申请号：US09373318

申请日：1999-08-12

申请人： Wan-Yih Lien ,  Meng-Jaw Cherng

发明人： Wan-Yih Lien ,  Meng-Jaw Cherng

IPC分类号： H01L213056

CPC分类号： H01L27/10855 ,  H01L21/31116 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L28/84 ,  H01L28/90

摘要： The invention describes a self-aligned etching process. A conductive layer and a first insulating layer are formed on a substrate in sequence, and then the conductive layer and the first insulating layer are patterned to form a plurality of stacks on desired regions. Subsequently, spacers are formed on sidewalls of each stack, and a stop layer is then formed on the substrate. A second insulating layer is formed on the substrate and is planarized. Portions of the second insulating layer are removed to form a plurality of openings and to expose portions of the stop layer located between spacers. The exposed stop layer is removed.

摘要翻译： 本发明描述了自对准蚀刻工艺。 依次在基板上形成导电层和第一绝缘层，然后将导电层和第一绝缘层图案化以在期望的区域上形成多个堆叠。 随后，在每个堆叠的侧壁上形成间隔物，然后在衬底上形成停止层。 在基板上形成第二绝缘层并进行平面化。 去除第二绝缘层的部分以形成多个开口并暴露位于间隔件之间的停止层的部分。 暴露的停止层被去除。

公开(公告)号：US5874359A

公开(公告)日：1999-02-23

申请号：US873828

申请日：1997-06-12

申请人： Ing-Ruey Liaw ,  Jau-Hwang Ho ,  Meng-Jaw Cherng

发明人： Ing-Ruey Liaw ,  Jau-Hwang Ho ,  Meng-Jaw Cherng

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485 ,  H01L21/44

CPC分类号： H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating very narrow contacts on semiconductor substrate for increasing the packing density of devices on Ultra Large Scale Integration (ULSI) circuits was achieved. The method involves using conventional photolithographic techniques and anisotropic plasma etching to etch openings in a conducting layer and partially etch into an underlying planar insulating layer that covers and isolates the devices and device contact areas. Another conformal conducting layer is deposited on the substrate and in the openings and then etched back to form sidewall spacers in the openings. Using the original conducting layer and the sidewall spacers as an etch mask, the planar insulating layer is anisotropically etched within the sidewall spacers to form very narrow (small) contact opening to the desired device contact areas. Still another conducting layer is then deposited to fill the very narrow contact openings making electrical contact to the device contact areas, and then the conducting layers are patterned to form the next level of connecting metallurgy.

摘要翻译： 实现了在半导体衬底上制造非常窄的触点的方法，用于提高超大规模集成（ULSI）电路上器件的封装密度。 该方法涉及使用常规光刻技术和各向异性等离子体蚀刻来蚀刻导电层中的开口并部分地蚀刻到覆盖和隔离器件和器件接触区域的下面的平坦绝缘层中。 另一个共形导电层沉积在基板上和开口中，然后回蚀刻以在开口中形成侧壁间隔物。 使用原始导电层和侧壁间隔物作为蚀刻掩模，平面绝缘层在侧壁间隔物内被各向异性地蚀刻，以形成到期望的器件接触区域的非常窄（小的）接触开口。 然后沉积另外的导电层以填充非常窄的接触开口，使得与器件接触区域电接触，然后将导电层图案化以形成下一级连接冶金。

公开(公告)号：US5719089A

公开(公告)日：1998-02-17

申请号：US668991

申请日：1996-06-21

申请人： Meng-Jaw Cherng ,  Pei-Wen Li

发明人： Meng-Jaw Cherng ,  Pei-Wen Li

IPC分类号： H01L21/3065 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/76816 ,  H01L21/3065 ,  Y10S438/947

摘要： A method for fabricating small contact openings in the polysilicon/metal 1 dielectric (PMD) layer on semiconductor substrates using polymer sidewall spacers was achieved. This extends the current photoresist resolution limits while simplifying the manufacturing process. The method involves depositing a polysilicon layer on the PMD layer and using a photoresist mask having openings over device contact areas in the substrate. The polysilicon layer is then patterned to form openings with vertical sidewalls to the PMD insulating layer. The contact openings are then anisotropically plasma etched in a gas mixture that simultaneously forms polymer sidewall spacers on the sidewalls in the openings in the polysilicon layer. These sidewall spacers further reduce the contact opening size. The remaining photoresist layer and polymer sidewall spacers are simultaneously removed to complete the narrow contact openings. This method eliminates the need to use an additional deposition and etch-back step to form the sidewalls. A metal layer is then deposited and patterned to form the metal contacts and first level of interconnections.

摘要翻译： 实现了使用聚合物侧壁间隔件在半导体衬底上的多晶硅/金属1电介质（PMD）层中制造小接触开口的方法。 这延长了当前的光刻胶分辨率限制，同时简化了制造工艺。 该方法包括在PMD层上沉积多晶硅层，并使用在衬底中的器件接触区域上具有开口的光致抗蚀剂掩模。 然后将多晶硅层图案化以形成具有垂直侧壁至PMD绝缘层的开口。 接触开口然后在气体混合物中各向异性等离子体蚀刻，同时在多晶硅层的开口中的侧壁上形成聚合物侧壁间隔物。 这些侧壁间隔件进一步减小接触开口尺寸。 同时去除剩余的光致抗蚀剂层和聚合物侧壁间隔物以完成窄的接触开口。 该方法不需要使用额外的沉积和回蚀步骤来形成侧壁。 然后沉积和图案化金属层以形成金属触点和第一级互连。

公开(公告)号：US5491104A

公开(公告)日：1996-02-13

申请号：US315555

申请日：1994-09-30

申请人： William W. Y. Lee ,  Meng-Jaw Cherng ,  Ing-Ruey Liaw

发明人： William W. Y. Lee ,  Meng-Jaw Cherng ,  Ing-Ruey Liaw

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87

摘要： An improved method for fabricating dynamic random access memory (DRAM) cell having a fin-shaped capacitor with increased capacitance was achieved. The capacitor is fabricated over the bit lines and makes contact to the source/drain area of a field effect transistor (FET). The capacitor with increased capacitance is formed by depositing an N doped polysilicon layer making electrical contact to the source/drain of the FET. A sacrificial oxide layer is deposited and a contact opening formed over the DRAM cell area to the polysilicon layer. A second polysilicon layer is deposited and patterned over the sacrificial oxide layer forming the top fin portion of the capacitor, which makes electrical contact to the first polysilicon layer through the contact opening. The sacrificial oxide layer is then completely removed by wet etching, while the underlying polysilicon layer provides a very important etch stop to protect the substrate structures. The top fin shaped portion of the capacitor is then used very effectively as a mask to anisotropically etch the bottom polysilicon layer, thereby forming a lower fin structure that is aligned to the top fin structure of the capacitor.

摘要翻译： 实现了具有具有增加的电容的鳍状电容器的动态随机存取存储器（DRAM）单元的改进方法。 电容器通过位线制造并与场效应晶体管（FET）的源极/漏极区域接触。 具有增加的电容的电容器通过沉积与FET的源极/漏极电接触的N掺杂多晶硅层而形成。 沉积牺牲氧化物层，并且在DRAM单元区域上形成的接触开口到多晶硅层。 在形成电容器的顶部翅片部分的牺牲氧化物层上沉积和图案化第二多晶硅层，其通过接触开口与第一多晶硅层电接触。 然后通过湿法蚀刻完全去除牺牲氧化物层，而下面的多晶硅层提供非常重要的蚀刻停止以保护衬底结构。 然后电容器的顶部翅片形状部分被非常有效地用作掩模以各向异性地蚀刻底部多晶硅层，从而形成与电容器的顶部翅片结构对准的下部翅片结构。

公开(公告)号：US06351037B1

公开(公告)日：2002-02-26

申请号：US09672763

申请日：2000-09-29

申请人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

发明人： Ing-Ruey Liaw ,  Meng-Jaw Cherng

IPC分类号： H01L2348

CPC分类号： H01L21/32053 ,  H01L21/32055

摘要： A method for making interlevel contacts having low contact resistance (Rc) between patterned polycide layers is described. The method and resulting contact structure consists of depositing and conductively doping a first polysilicon layer having a first tungsten silicide (WSi2) layer. The first polysilicon/silicide (first polycide) layer is patterned to form the first polycide inter connecting conducting layer. An insulating layer is deposited over the patterned first polycide layer and contact openings are anisotropically plasma etched in the insulating layer to the underlying polycide layer. The etching is continued to remove completely the first silicide layer in the contact openings, and to etch into the first polysilicon-layer. After a brief hydrofluoric (HF) etch, a second doped polysilicon layer is deposited and patterned to form a second conducting interconnecting level over the contact openings. The second polysilicon-to-first polysilicon interface formed in the contacts results in consistently low contact resistance (Rc). This low Rc is difficult to achieve in the prior art where the second level metallurgy contacts the first tungsten silicide of the first level interconnecting polycide layer.

摘要翻译： 描述了在图案化的多晶硅化物层之间制造具有低接触电阻（Rc）的层间接触的方法。 该方法和所得的接触结构包括沉积和电导掺杂具有第一硅化钨（WSi2）层的第一多晶硅层。 将第一多晶硅/硅化物（第一多晶硅）层图案化以形成第一多晶硅互连导电层。 在图案化的第一多晶硅化物层上沉积绝缘层，并且将绝缘层中的各向异性等离子体蚀刻接触开口到下面的多晶硅化物层。 蚀刻继续完全去除接触开口中的第一硅化物层，并蚀刻入第一多晶硅层。 在短暂的氢氟酸（HF）蚀刻之后，沉积第二掺杂多晶硅层并图案化以在接触开口上形成第二导电互连层。 在触点中形成的第二多晶硅到第一多晶硅界面导致一致的低接触电阻（Rc）。 这种低Rc在现有技术中难以实现，其中第二级冶金接触第一级互连多晶硅化物层的第一硅化钨。

公开(公告)号：US06174781B1

公开(公告)日：2001-01-16

申请号：US09342569

申请日：1999-06-29

申请人： Chang-Ming Dai ,  Meng-Jaw Cherng

发明人： Chang-Ming Dai ,  Meng-Jaw Cherng

IPC分类号： H01L2120

CPC分类号： H01L28/60

摘要： A method of fabricating a capacitor is described in which a substrate comprises a transistor and a planarized insulation layer. An opening is formed in the insulation layer, exposing one of the source/drain of the transistor. A sacrificial plug is formed in the first opening. The insulation layer surrounding the first opening is removed to form a second opening and a certain thickness of the insulation layer is retained at the bottom of the second opening. The sacrificial plug is removed and simultaneously forming a node plug and a first electrode respectively in the first opening and on the bottom and side wall of the second opening. A dielectric layer is further formed on the surface of the first electrode and a second electrode is formed on the dielectric layer.

摘要翻译： 描述制造电容器的方法，其中衬底包括晶体管和平坦化绝缘层。 在绝缘层中形成开口，暴露晶体管的源/漏之一。 牺牲塞形成在第一开口中。 围绕第一开口的绝缘层被去除以形成第二开口，并且绝缘层的一定厚度保持在第二开口的底部。 除去牺牲塞，同时分别在第一开口和第二开口的底壁和侧壁上形成节点塞和第一电极。 在第一电极的表面上进一步形成电介质层，在电介质层上形成第二电极。