公开(公告)号：US6097041A

公开(公告)日：2000-08-01

申请号：US138992

申请日：1998-08-24

Applicant: Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

Inventor： Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

IPC: H01L33/10 ,  H01L33/00

CPC classification number: H01L33/105

Abstract: A light emitting diode includes a semiconductor substrate of a first conductivity type. A first electrode is formed on a part of the substrate. A reflection stack of the first conductivity type is formed on the substrate. An active layer is then formed on the reflection stack. An anti-reflection stack of a second conductivity type is grown on the active layer, and the anti-reflection stack consists of a plurality of layers, wherein each layer has a thickness of (m+1).lambda./2, where m is zero or a positive integer and .lambda. is a wavelength of radiation generated by the active layer. A window layer of the second conductivity type is formed on the anti-reflection stack. A second electrode is then formed on a part of the window layer.

Abstract translation: 发光二极管包括第一导电类型的半导体衬底。 第一电极形成在基板的一部分上。 在基板上形成第一导电类型的反射叠层。 然后在反射叠层上形成有源层。 在有源层上生长第二导电类型的抗反射叠层，并且抗反射叠层由多个层组成，其中每层具有（m + 1）λ/ 2的厚度，其中m为零 或正整数，λ是由有源层产生的辐射的波长。 第二导电类型的窗口层形成在防反射叠层上。 然后在窗口层的一部分上形成第二电极。

公开(公告)号：US6004877A

公开(公告)日：1999-12-21

申请号：US31259

申请日：1998-02-26

Applicant: Tony Liang-Tung Chang ,  Shiang-Peng Cheng

Inventor： Tony Liang-Tung Chang ,  Shiang-Peng Cheng

IPC: C23C16/14 ,  C23C16/56 ,  H01L21/02 ,  H01L21/285 ,  H01L21/4763

CPC classification number: H01L21/28568 ,  C23C16/14 ,  C23C16/56 ,  H01L21/28556 ,  H01L28/75

Abstract: A titanium layer is formed on a dielectric layer. A TiN layer is formed on the titanium layer to act as a barrier layer. A rapid thermal annealing is performed. A tungsten layer is deposited by useing chemical vapor deposition with N.sub.2 plasma treatment. In a preferred embodiment, the temperature of the deposition ranges from 300 to 500 degrees centigrade. The gas pressure of the process is about 2 to 4 torr. The power of the plasma is about 300 to 800 Further, the treatment time of the N.sub.2 plasma ranges from 50 to 150 seconds. An etching back step is carried to etch a portion of the tuugsten layer.

Abstract translation: 在电介质层上形成钛层。 在钛层上形成TiN层作为阻挡层。 进行快速热退火。 通过使用化学气相沉积与N 2等离子体处理来沉积钨层。 在优选的实施方案中，沉积温度范围为300-500摄氏度。 该工艺的气体压力约为2至4托。 等离子体的功率为约300〜800。另外，N2等离子体的处理时间为50〜150秒。 进行蚀刻后续步骤以蚀刻钨钢层的一部分。

公开(公告)号：US5962344A

公开(公告)日：1999-10-05

申请号：US999229

申请日：1997-12-29

Applicant: Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

Inventor： Yeur-Luen Tu ,  Shiang-Peng Cheng ,  Kwong-Jr Tsai ,  Liang-Gi Yao

IPC: H01L21/318 ,  H01L21/441

CPC classification number: H01L21/3185

Abstract: A plasma treatment method used to form improved PECVD silicon nitride film passivation layers over metal interconnections on ULSI circuits is achieved. The process is carried out in a single PECVD reactor. After depositing a thin silicon oxide stress-release layer over the metal lines, a plasma-enhanced CVD silicon nitride layer is deposited, and subsequently a plasma treatment step is carried out on the silicon nitride layer. The use of a sufficiently thin silicon nitride layer eliminates photoresist trapping at the next photoresist process step that would otherwise be trapped in the voids (keyholes) that typically form in the silicon nitride passivation layer between the closely spaced metal lines, and can cause corrosion of the metal. The plasma treatment in He, Ar, or a mixture of the two, is then used to densify the silicon nitride layer and to substantially reduce pinholes that would otherwise cause interlevel metal shorts.

Abstract translation: 实现了用于在ULSI电路上的金属互连上形成改进的PECVD氮化硅膜钝化层的等离子体处理方法。 该过程在单个PECVD反应器中进行。 在金属线上沉积薄氧化硅应力释放层之后，沉积等离子体增强的CVD氮化硅层，随后在氮化硅层上进行等离子体处理步骤。 使用足够薄的氮化硅层在下一个光刻胶工艺步骤消除光致抗蚀剂捕获，否则将被捕获在通常在紧密间隔的金属线之间的氮化硅钝化层中形成的空隙（键槽）中，并且可能导致腐蚀 金属。 然后，使用He，Ar中的等离子体处理或两者的混合物来使氮化硅层致密化并且基本上减少否则将引起层间金属短路的针孔。

公开(公告)号：US6103639A

公开(公告)日：2000-08-15

申请号：US984354

申请日：1997-12-03

Applicant: Tony Chang ,  Shiang-Peng Cheng

Inventor： Tony Chang ,  Shiang-Peng Cheng

IPC: C23C16/42 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/522 ,  H01L21/31

CPC classification number: H01L21/3185 ,  H01L21/31612

Abstract: A metal interconnection is formed on a dielectric layer. A pre-treatment is then performed to remove organic materials on the surface of the metal layer. The pre-treatment is done by plasma bombardment using NH.sub.3 and NO.sub.2 as the reaction gases. A thin oxide layer is subsequently deposited on the metal layer and on the dielectric layer. The oxide layer serves a buffer layer to eliminate the stress between the metal layer and subsequent silicon nitride layer. A silicon nitride layer is then formed on the thin oxide layer to act as a passivation layer.

Abstract translation: 金属互连形成在电介质层上。 然后进行预处理以除去金属层表面上的有机材料。 预处理通过使用NH 3和NO 2作为反应气体的等离子体轰击进行。 随后在金属层和电介质层上沉积薄的氧化物层。 氧化物层用于缓冲层以消除金属层和随后的氮化硅层之间的应力。 然后在薄氧化物层上形成氮化硅层以用作钝化层。

公开(公告)号：US5851603A

公开(公告)日：1998-12-22

申请号：US891910

申请日：1997-07-14

Applicant: Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

Inventor： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B05D3/06

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

Abstract translation: 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。

公开(公告)号：US06169298A

公开(公告)日：2001-01-02

申请号：US09131727

申请日：1998-08-10

Applicant: Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

Inventor： Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

IPC: H01L3300

CPC classification number: H01L33/02 ,  H01L33/14 ,  H01L33/30

Abstract: A semiconductor light emitting device, such as the light emitting diode (LED) or the laser diode (LD), having a structure in which a light emitting area is a double heterostructure or a multi-layer quantum well structure. The light emitting area is formed on a substrate. Subsequently, an electrically conductive oxide layer as a transparent window layer to eliminate the crowding effect is formed on the light emitting area. The substrate layer consists of a GaAs substrate and a GaAsP layer to increasing the band gap energy of the substrate. The electrically conductive oxide layer is formed of AlZnO(x) material, having a lower electrical resistivity and a high transparency in the visible wavelength region. The window layer is formed using a physical vapor deposition or a metalorganic chemical vapor deposition.

Abstract translation: 诸如发光二极管（LED）或激光二极管（LD）的半导体发光器件具有其中发光区域是双异质结构或多层量子阱结构的结构。 发光区域形成在基板上。 随后，在发光区域上形成作为透明窗口层的导电氧化物层以消除拥挤效应。 衬底层由GaAs衬底和GaAsP层组成，以增加衬底的带隙能量。 导电氧化物层由AlZnO（x）材料形成，具有较低的电阻率和可见光波长区域的高透明度。 窗层使用物理气相沉积或金属有机化学气相沉积形成。

公开(公告)号：US6017614A

公开(公告)日：2000-01-25

申请号：US157510

申请日：1998-09-21

Applicant: Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

Inventor： Kwong-Jr Tsai ,  Shiang-Peng Cheng ,  Yeur-Luen Tu ,  Ing-Ruey Liaw

IPC: H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L23/532 ,  B32B3/00

CPC classification number: H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/3185 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5329 ,  H01L21/76837 ,  H01L2924/0002 ,  Y10S438/938 ,  Y10T428/24917

Abstract: A method was achieved for forming a multilayer passivation layer comprised of a silicon oxide/silicon nitride/silicon oxide/silicon nitride by depositing the layers consecutively in a single PECVD system. The method consists of depositing a first SiO.sub.2 layer that serves as a stress-release layer, a thin Si.sub.3 N.sub.4 layer that serves as a buffer layer that minimizes cracking and as a passivation layer that prevents mobile alkaline ion penetration, a thin second SiO.sub.2 layer to fill and seal any remaining cracks and pinholes in the first Si.sub.3 N.sub.4 layer, and a main Si.sub.3 N.sub.4 passivation layer that prevents water and/or other corrosive chemicals from attacking the metal. Since this multilayer passivation layer can be deposited essentially pinhole-free to a thickness that is less than the prior art's passivation layer of 8000 Angstroms needed to prevent pinholes, it can be used on 0.38 to 0.25 um DRAM technology, which eliminates voids that could otherwise trap photoresist which can later cause corrosion of the metal lines.

Abstract translation: 通过在单个PECVD系统中连续沉积层来形成由氧化硅/氮化硅/氧化硅/氮化硅组成的多层钝化层的方法。 该方法包括沉积用作应力释放层的第一SiO 2层，用作最小化裂纹的缓冲层的薄Si 3 N 4层，以及防止移动碱性离子渗透的钝化层，稀的第二SiO 2层填充 并且密封第一Si 3 N 4层中的任何剩余的裂纹和针孔，以及防止水和/或其它腐蚀性化学物质侵蚀金属的主要Si 3 N 4钝化层。 由于这种多层钝化层可以基本上无针孔地沉积到比现有技术的防止针孔所需的8000埃的钝化层的厚度，所以它可以用于0.38到0.25微米的DRAM技术，这消除了否则的空隙 陷阱光致抗蚀剂可以后来导致金属线的腐蚀。

公开(公告)号：US06008507A

公开(公告)日：1999-12-28

申请号：US144908

申请日：1998-09-01

Applicant: Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

Inventor： Ying-Fu Lin ,  Liang-Tung Chang ,  Shiang-Peng Cheng ,  Kuan-Chu Kuo ,  Chiao-Yun Lin ,  Fu-Chou Liu

IPC: H01L33/10 ,  H01L33/30 ,  H01L33/00 ,  H01L31/0328

CPC classification number: H01L33/30 ,  H01L33/10

Abstract: A structure of a semiconductor light emitting device includes a GaAs substrate, a GaAsP interface substrate, a first cladding layer, an active layer, and a second cladding layer. The GaAsP interface substrate layer is formed on the GaAs substrate, in addition, the GaAsP interface substrate layer formed on the substrate is of a thickness such that the upper surface of the GaAsP interface substrate layer adjacent to the substrate is composed of single crystal. The first cladding layer of a first conductivity is formed on the GaAsP interface substrate layer. The active layer is formed on the first cladding layer, from which the light is generated in the active layer. The second cladding layer of a second conductivity is formed on the active layer.

Abstract translation: 半导体发光器件的结构包括GaAs衬底，GaAsP界面衬底，第一覆层，有源层和第二覆层。 在GaAs衬底上形成GaAsP界面衬底层，此外，形成在衬底上的GaAsP界面衬底层的厚度使得与衬底相邻的GaAsP界面衬底层的上表面由单晶构成。 在GaAsP界面基底层上形成第一导电性的第一覆层。 活性层形成在第一包覆层上，在活性层中产生光。 在有源层上形成第二导电性的第二覆层。