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    Flexible filter logic for multi-mode filtering of graphical texture data
    1.
    发明授权
    Flexible filter logic for multi-mode filtering of graphical texture data 有权
    灵活的滤波器逻辑，用于图形纹理数据的多模式滤波

    公开(公告)号：US09367948B2

    公开(公告)日：2016-06-14

    申请号：US14080441

    申请日：2013-11-14

    申请人： Liang Peng ,  Yoav Harel ,  Steven Spangler

    发明人： Liang Peng ,  Yoav Harel ,  Steven Spangler

    IPC分类号： G09G5/00 ,  G06T15/04 ,  G06T11/00 ,  G06T1/60

    CPC分类号： G06T15/04 ,  G06T1/60 ,  G06T11/001

    摘要： Multi-mode texture filters suitable for performing both bilinear filtering based on a fractional texture address and generating a weighted average of a group of texel values based on predetermined texel weighting coefficients as dependent on a filter mode signal. In embodiments, the weighted average may be accumulated over a variety of filter footprints. In embodiments, multi-mode texture filter logic includes a plurality of flexible filter blocks. In further embodiments, a pair of flexible filter blocks staged with each performing one lerp phase in the bilinear filter mode while a pair of flexible filter blocks in the flexible filter mode generate a weighted average over a pair of texels of a texel quad. In embodiments, each flexible filter block has a same microarchitecture, enabling an efficient utilization in either bilinear filter or flexible filter mode.

    摘要翻译： 适合于基于分数纹理地址执行双线性滤波的多模式纹理滤波器，并且基于取决于滤波器模式信号的预定纹素加权系数，生成一组纹素值的​​加权平均值。 在实施例中，加权平均值可以在各种滤波器覆盖区上累积。 在实施例中，多模式纹理滤波器逻辑包括多个柔性滤波器块。 在另外的实施例中，一对柔性滤波器块以每个以双线性滤波器模式执行一个lerp相位分阶段，而在柔性滤波器模式中的一对柔性滤波器块在纹素四边形的一对纹素上产生加权平均。 在实施例中，每个柔性滤波器块具有相同的微架构，能够以双线性滤波器或柔性滤波器模式有效利用。

    LAND GRID ARRAY SOCKET FOR ELECTRO-OPTICAL MODULES
    2.
    发明申请
    LAND GRID ARRAY SOCKET FOR ELECTRO-OPTICAL MODULES 有权
    用于电光模块的LAND网格阵列插座

    公开(公告)号：US20150130826A1

    公开(公告)日：2015-05-14

    申请号：US14080357

    申请日：2013-11-14

    申请人： Liang Peng ,  Steven Spangler

    发明人： Liang Peng ,  Steven Spangler

    IPC分类号： G06T15/04 ,  G06T1/60 ,  G06T15/00

    CPC分类号： G06T15/04 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2200/04 ,  G06T2200/28

    摘要： For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints in either a separable or non-separable filter modes and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, sub-sample addresses are generated by the texture sampler logic to accommodate a desired footprint. The sub-sample addresses may be generated and sequenced by multi-texel units, such as 2×2 texel quads, for efficient filtering. In embodiments, filter coefficients are cached from coefficient tables stored in memory.

    摘要翻译： 对于给定的纹理地址，纹理采样器使用过滤器累加器来获取和减少纹理数据，该过滤器累加器适用于通过各种过滤器覆盖区提供加权平均值。 多模式纹理采样器可配置为以可分离或不可分离的滤波器模式提供各种各样的覆盖区域，并允许比双线性（2×2纹素）覆盖区域更宽的滤波器占用空间。 在实施例中，子样本地址由纹理采样器逻辑生成以适应期望的覆盖区。 子样本地址可以通过多纹素单元（例如2×2纹素四边形）生成和排序，用于有效过滤。 在实施例中，滤波器系数从存储在存储器中的系数表缓存。

    ATOMIC MEMORY DEVICE
    3.
    发明申请
    ATOMIC MEMORY DEVICE 审中-公开
    原子记忆装置

    公开(公告)号：US20120117317A1

    公开(公告)日：2012-05-10

    申请号：US13383205

    申请日：2010-06-17

    申请人： Thomas Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    发明人： Thomas Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    IPC分类号： G06F12/00

    CPC分类号： G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107 ,  H05K999/99

    摘要： In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command.

    摘要翻译： 在具有存储器核心的集成电路存储器件中，响应于存储器访问命令，从存储器内核中的地址指定位置检索第一数据值。 响应于存储器访问命令，从存储器件输出第一数据值，并且响应于存储器访问命令将第二数据值存储在存储器内核中的地址指定位置中。

    ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS
    5.
    发明申请
    ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS 有权
    多芯片系统中的原理操作技术

    公开(公告)号：US20110289510A1

    公开(公告)日：2011-11-24

    申请号：US13143993

    申请日：2010-02-02

    申请人： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

    发明人： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

    IPC分类号： G06F9/46

    CPC分类号： G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

    摘要： A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

    摘要翻译： 缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

    RENDERING DYNAMIC OBJECTS USING GEOMETRY LEVEL-OF-DETAIL IN A GRAPHICS PROCESSING UNIT
    7.
    发明申请
    RENDERING DYNAMIC OBJECTS USING GEOMETRY LEVEL-OF-DETAIL IN A GRAPHICS PROCESSING UNIT 审中-公开
    在图形处理单元中使用几何级别的渲染动态对象

    公开(公告)号：US20090195541A1

    公开(公告)日：2009-08-06

    申请号：US12362122

    申请日：2009-01-29

    申请人： Liang Peng ,  Yixhou Yu ,  Wei-Wen Feng

    发明人： Liang Peng ,  Yixhou Yu ,  Wei-Wen Feng

    IPC分类号： G06T17/00

    CPC分类号： G06T17/20 ,  G06T15/005 ,  G06T2210/08 ,  G06T2210/12 ,  G06T2210/36

    摘要： The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through superposition of object motions in each frame weighted by a set of predetermined mesh-skinning parameters. For each deformed bounding box, the system computes a geometry level-of-detail (LOD) value based on a projected area of the deformed bounding box in screen space. The system next deforms the object through a set of mesh skinning operations. The system then renders the deformed object based on the computed geometry LOD values for the set of patches and the multi-resolution representation for the geometry mesh.

    摘要翻译： 本实施例提供了用于图形化呈现对象的系统。 该系统首先通过对离线对象的几何网格进行预处理，其中几何网格被分割成一组补丁，并且其中每个补丁由边界框限定。 然后，系统为每组补丁构建多分辨率表示。 接下来，在实时呈现期间，系统通过在由一组预定的网格划分参数加权的每个帧中的对象运动的叠加来使与该组补丁相关联的边界框变形。 对于每个变形的边界框，系统基于屏幕空间中变形的边界框的投影面积来计算几何细节级别（LOD）值。 系统接着通过一组网格去皮操作来变形对象。 然后，该系统基于用于几何网格的一组补丁的计算几何LOD值和多分辨率表示来呈现变形对象。

    Aiding in a satellite positioning system
    8.
    发明授权
    Aiding in a satellite positioning system 有权
    协助卫星定位系统

    公开(公告)号：US07236883B2

    公开(公告)日：2007-06-26

    申请号：US10515808

    申请日：2003-12-04

    申请人： Lionel Jacques Garin ,  Leon Kuo-Liang Peng ,  Gengsheng Zhang ,  Nicolas Patrick Vantalon

    发明人： Lionel Jacques Garin ,  Leon Kuo-Liang Peng ,  Gengsheng Zhang ,  Nicolas Patrick Vantalon

    IPC分类号： G01C21/00

    CPC分类号： G01S19/256 ,  G01S19/235 ,  G01S19/254

    摘要： The invention relates to an aided Global Positioning System (GPS) subsystem within a wireless device. The wireless device includes a wireless processing section capable of receiving signals from a wireless network and a GPS subsystem having a radio frequency (RF) front-end capable of receiving a GPS satellite signal. The wireless processing section of the wireless device receives an external clock and determines the offset between the clock in the wireless processing section and that of the external clock. The GPS subsystem then receives the offset information from the wireless processing section, information related to the nominal frequency of the wireless processing section clock and the wireless processing section clock. Using this information and the GPS clock in the GPS subsystem, the GPS subsystem determines an acquiring signal, which is related to a frequency offset between the GPS clock and the network clock. The GPS subsystem then acquires GPS satellite signals in an acquiring unit though the use of the acquiring signal.

    摘要翻译： 本发明涉及无线设备内的辅助全球定位系统（GPS）子系统。 无线设备包括能够从无线网络接收信号的无线处理部分和具有能够接收GPS卫星信号的射频（RF）前端的GPS子系统。 无线装置的无线处理部接收外部时钟并确定无线处理部中的时钟与外部时钟的时钟之间的偏移。 然后，GPS子系统接收来自无线处理部分的偏移信息，与无线处理部分时钟的标称频率和无线处理部分时钟有关的信息。 在GPS子系统中使用该信息和GPS时钟，GPS子系统确定与GPS时钟和网络时钟之间的频率偏移相关的获取信号。 然后，GPS子系统通过使用采集信号在获取单元中获取GPS卫星信号。

    Tracker architecture for GPS systems
    9.
    发明授权
    Tracker architecture for GPS systems 有权
    GPS系统的跟踪器架构

    公开(公告)号：US07091904B2

    公开(公告)日：2006-08-15

    申请号：US10199253

    申请日：2002-07-18

    申请人： Nicolas Vantalon ,  Leon Kuo-Liang Peng ,  Gregory Turetzky

    发明人： Nicolas Vantalon ,  Leon Kuo-Liang Peng ,  Gregory Turetzky

    IPC分类号： G01S5/14 ,  G06F15/163

    CPC分类号： G01S19/37 ,  G01S19/34 ,  G01S19/35 ,  G01S19/46

    摘要： A tracker architecture for Global Positioning System (GPS) receivers is disclosed. A typical tracker comprises an RF front end and GPS architecture. The architecture comprises a bus structure, a Central Processing Unit (CPU) core, cache, RAM, and ROM memories, and a GPS engine that comprises a receiving, tracking, and demodulating engine for GPS and Wide Area Augmentation Service (WAAS) signals. The GPS architecture can couple to at least two different protocol interfaces via the bus structure, where the protocol interfaces are commonly used in different applications.

    摘要翻译： 公开了全球定位系统（GPS）接收机的跟踪架构。 典型的跟踪器包括RF前端和GPS架构。 该架构包括总线结构，中央处理单元（CPU）核心，高速缓存，RAM和ROM存储器，以及包括用于GPS和广域增强服务（WAAS）信号的接收，跟踪和解调引擎的GPS引擎。 GPS架构可以通过总线结构耦合到至少两个不同的协议接口，其中协议接口通常用于不同的应用。

    Shared memory architecture in GPS signal processing
    10.
    发明授权
    Shared memory architecture in GPS signal processing 有权

    公开(公告)号：US06930634B2

    公开(公告)日：2005-08-16

    申请号：US10309647

    申请日：2002-12-04

    申请人： Leon Kuo-Liang Peng ,  Henry D. Falk

    发明人： Leon Kuo-Liang Peng ,  Henry D. Falk

    IPC分类号： G01S1/00 ,  G06F12/00

    CPC分类号： G01S19/24 ,  G01S19/29 ,  G01S19/37

    摘要： A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.