利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

5 条记录 (耗时 0.01 秒)

    Method of manufacturing an insulated gate field effect transistor
    2.
    发明授权
    Method of manufacturing an insulated gate field effect transistor 失效
    绝缘栅场效应晶体管的制造方法

    公开(公告)号：US5824580A

    公开(公告)日：1998-10-20

    申请号：US688346

    申请日：1996-07-30

    申请人： Manfred Hauf ,  Max G. Levy ,  Victor Ray Nastasi

    发明人： Manfred Hauf ,  Max G. Levy ,  Victor Ray Nastasi

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： A Field Effect Transistor (FET) and a method of forming FETs on a silicon wafer. First, trenches are formed in a surface of the silicon wafer. An ONO layer is formed on the surface, lining the trenches. Potassium is diffused along the ONO layer. Part of the ONO layer is removed to expose the wafer surface with the ONO layer remaining in the trenches. A gate oxide is formed on the exposed wafer surface. Finally, FET gates are formed on the gate oxide. Preferably, potassium is introduced during Chem-Mech polish when the trenches are filled with polysilicon. A slurry containing KOH is used to polish the polysilicon and the potassium diffuses from the slurry along the ONO layer. After Chem-Mech polish, the poly in the trenches is recessed by Reactive Ion Etching (RIE) it below the wafer surface. Optionally, after RIE, the wafer may be dipped in a KOH solution. Next, an oxide collar is formed along the ONO layer in the trenches above the recessed polysilicon. The recesses are filled by a second layer of polysilicon that is Chem-Mech polished with the same slurry to remove polysilicon from the wafer surface. The polished polysilicon may be Reactive Ion etched until it is essentially coplanar with the wafer surface. The resulting FET has thicker gate oxide along its sides than in the center of its channel.

    摘要翻译： 场效应晶体管（FET）和在硅晶片上形成FET的方法。 首先，在硅晶片的表面形成沟槽。 在表面上形成ONO层，衬在沟槽上。 钾沿着ONO层扩散。 除去ONO层的一部分以露出晶片表面，其中ONO层保留在沟槽中。 在暴露的晶片表面上形成栅极氧化物。 最后，FET栅极形成在栅极氧化物上。 当化学工业抛光时，当沟槽充满多晶硅时，优选引入钾。 使用含有KOH的浆料来抛光多晶硅并且沿着ONO层从浆料中扩散钾。 化学磨光后，沟槽中的多晶硅通过晶片表面下方的反应离子蚀刻（RIE）凹陷。 任选地，在RIE之后，晶片可以浸入KOH溶液中。 接下来，在凹陷多晶硅上方的沟槽中沿着ONO层形成氧化物环。 这些凹槽由Chem-Mech用相同浆料抛光的第二层多晶硅填充，以从晶片表面去除多晶硅。 抛光的多晶硅可以是反应离子蚀刻，直到其基本上与晶片表面共面。 所产生的FET沿其侧面具有比其通道中心更厚的栅极氧化物。