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122 条记录 (耗时 0.045 秒)

    Method for surface roughness enhancement in semiconductor capacitor manufacturing
    2.
    发明授权
    Method for surface roughness enhancement in semiconductor capacitor manufacturing 失效
    半导体电容器制造中表面粗糙度增强的方法

    公开(公告)号：US06613642B2

    公开(公告)日：2003-09-02

    申请号：US10016075

    申请日：2001-12-13

    申请人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

    发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

    IPC分类号： H01L2120

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

    摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

    摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

    Process flow for capacitance enhancement in a DRAM trench
    3.
    发明授权
    Process flow for capacitance enhancement in a DRAM trench 失效
    DRAM沟槽中电容增强的工艺流程

    公开(公告)号：US06555430B1

    公开(公告)日：2003-04-29

    申请号：US09723420

    申请日：2000-11-28

    申请人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    发明人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

    IPC分类号： H01L218242

    CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/964

    摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

    摘要翻译： 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

    Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability
    4.
    发明授权
    Variable stoichiometry silicon nitride barrier films for tunable etch selectivity and enhanced hyrogen permeability 有权
    用于可调蚀刻选择性和增强的透氢性的可变化学计量氮化硅阻挡膜

    公开(公告)号：US06268299B1

    公开(公告)日：2001-07-31

    申请号：US09668988

    申请日：2000-09-25

    申请人： Rajarao Jammy ,  Johnathan E. Faltermeier ,  Keitaro Imai ,  Ryota Katsumata ,  Jean-Marc Rousseau ,  Viraj Y. Sardesai ,  Joseph F. Shepard, Jr.

    发明人： Rajarao Jammy ,  Johnathan E. Faltermeier ,  Keitaro Imai ,  Ryota Katsumata ,  Jean-Marc Rousseau ,  Viraj Y. Sardesai ,  Joseph F. Shepard, Jr.

    IPC分类号： H01L21318

    CPC分类号： C23C14/0652 ,  H01L21/3185

    摘要： A low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD). The process includes the following steps. First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane, and mixtures of those compositions. The ratio of the volume of ammonia to the volume of the silicon-containing gas is adjusted to yield silicon concentrations greater than 43 atomic percent in the resultant film. The process applies a deposition temperature of 550° C. to 720° C. The ammonia and the silicon-containing gas are reacted at the deposition temperature to form a silicon-rich nitride film less than 200 Å thick. Finally, the silicon nitride film is deposited by low pressure chemical vapor deposition.

    摘要翻译： 在低压化学气相沉积（LPCVD）的集成电路制造过程中形成高保形阻挡膜的低温工艺。 该过程包括以下步骤。 首先，该方法提供氨和含硅气体，其选自硅烷，二氯硅烷，二丁基氨基硅烷，六氯二硅烷，以及这些组合物的混合物。 调节氨体积与含硅气体体积的比例，得到所得膜中硅浓度大于43原子百分比。 该方法将沉积温度为550℃至720℃。氨和含硅气体在沉积温度下反应，形成厚度小于200埃的富硅氮化物膜。 最后，通过低压化学气相沉积沉积氮化硅膜。

    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
    8.
    发明授权
    Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
    用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构

    公开(公告)号：US06936512B2

    公开(公告)日：2005-08-30

    申请号：US10260085

    申请日：2002-09-27

    申请人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    发明人： Michael P. Chudzik ,  Rajarao Jammy ,  Carl John Radens ,  Kenneth T. Settlemyer, Jr. ,  Padraic Shafer ,  Joseph F. Shepard, Jr.

    IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L29/66181 ,  H01L21/3144 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L27/10864 ,  H01L27/10867

    摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.

    摘要翻译： 本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。 所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。 然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸 。 然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极 使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。 在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。