Semiconductor device for electron emission in a vacuum
    2.
    发明授权
    Semiconductor device for electron emission in a vacuum 有权
    用于真空中电子发射的半导体器件

    公开(公告)号:US09305734B2

    公开(公告)日:2016-04-05

    申请号:US14234328

    申请日:2012-07-20

    IPC分类号: H01J1/308 H01J23/04

    CPC分类号: H01J1/308 H01J23/04

    摘要: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

    摘要翻译: 用于真空中电子发射的半导体器件包括根据序列N /(P)/ N的两个或多个N型和P型半导体层的堆叠,形成两个头对尾NP连接的并置,材料 属于III-N族,两个相邻的层形成界面。 靠近真空的堆叠层的半导体材料,其中电子达到高能量,具有带隙Eg> c / 2,其中c是半导体材料的电子亲和力,P型半导体层是 通过掺杂受体类型的杂质或通过压电效应来获得部分或完全地获得,以在层之间的任何界面中显示负的固定电荷,施加到堆叠的积极偏置电势提供给堆叠中循环的一部分电子, 需要通过输出层的发射区在真空中发射。

    SEMICONDUCTOR DEVICE FOR ELECTRON EMISSION IN A VACUUM
    3.
    发明申请
    SEMICONDUCTOR DEVICE FOR ELECTRON EMISSION IN A VACUUM 有权
    用于真空中电子发射的半导体器件

    公开(公告)号:US20140326943A1

    公开(公告)日:2014-11-06

    申请号:US14234328

    申请日:2012-07-20

    IPC分类号: H01J1/308

    CPC分类号: H01J1/308 H01J23/04

    摘要: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

    摘要翻译: 用于真空中电子发射的半导体器件包括根据序列N /(P)/ N的两个或多个N型和P型半导体层的堆叠,形成两个头对尾NP结的并置,材料 属于III-N族,两个相邻的层形成界面。 靠近真空的堆叠层的半导体材料,其中电子达到高能量,具有带隙Eg> c / 2,其中c是半导体材料的电子亲和力,P型半导体层是 通过掺杂受体类型的杂质或通过压电效应来获得部分或完全地获得,以在层之间的任何界面中显示负的固定电荷,施加到堆叠的积极偏置电势提供给堆叠中循环的一部分电子, 需要通过输出层的发射区在真空中发射。

    Method for the making of the electrode metallizations of a transistor
    4.
    发明授权
    Method for the making of the electrode metallizations of a transistor 失效
    制造晶体管电极金属化的方法

    公开(公告)号:US5194403A

    公开(公告)日:1993-03-16

    申请号:US769837

    申请日:1991-10-02

    摘要: The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.

    摘要翻译: 该方法的目的是防止凸起图案的侧壁上的寄生金属化,其用于自对准晶体管中的电极金属化。 为此,将一对半导体材料引入垂直图案。 这些半导体材料相对于一对蚀刻方法反应不同,使得一层半导体材料的层被蚀刻到比另一层更大的程度。 由此产生的突出特征中断了电极之间的寄生金属化(如果有的话)。 所公开的方法可以应用于垂直结构。