SEMICONDUCTOR DEVICE FOR ELECTRON EMISSION IN A VACUUM
    2.
    发明申请
    SEMICONDUCTOR DEVICE FOR ELECTRON EMISSION IN A VACUUM 有权
    用于真空中电子发射的半导体器件

    公开(公告)号:US20140326943A1

    公开(公告)日:2014-11-06

    申请号:US14234328

    申请日:2012-07-20

    IPC分类号: H01J1/308

    CPC分类号: H01J1/308 H01J23/04

    摘要: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

    摘要翻译: 用于真空中电子发射的半导体器件包括根据序列N /(P)/ N的两个或多个N型和P型半导体层的堆叠,形成两个头对尾NP结的并置,材料 属于III-N族,两个相邻的层形成界面。 靠近真空的堆叠层的半导体材料,其中电子达到高能量,具有带隙Eg> c / 2,其中c是半导体材料的电子亲和力,P型半导体层是 通过掺杂受体类型的杂质或通过压电效应来获得部分或完全地获得,以在层之间的任何界面中显示负的固定电荷,施加到堆叠的积极偏置电势提供给堆叠中循环的一部分电子, 需要通过输出层的发射区在真空中发射。

    Method for the making of the electrode metallizations of a transistor
    3.
    发明授权
    Method for the making of the electrode metallizations of a transistor 失效
    制造晶体管电极金属化的方法

    公开(公告)号:US5194403A

    公开(公告)日:1993-03-16

    申请号:US769837

    申请日:1991-10-02

    摘要: The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.

    摘要翻译: 该方法的目的是防止凸起图案的侧壁上的寄生金属化,其用于自对准晶体管中的电极金属化。 为此,将一对半导体材料引入垂直图案。 这些半导体材料相对于一对蚀刻方法反应不同,使得一层半导体材料的层被蚀刻到比另一层更大的程度。 由此产生的突出特征中断了电极之间的寄生金属化(如果有的话)。 所公开的方法可以应用于垂直结构。

    Semiconductor device for electron emission in a vacuum
    4.
    发明授权
    Semiconductor device for electron emission in a vacuum 有权
    用于真空中电子发射的半导体器件

    公开(公告)号:US09305734B2

    公开(公告)日:2016-04-05

    申请号:US14234328

    申请日:2012-07-20

    IPC分类号: H01J1/308 H01J23/04

    CPC分类号: H01J1/308 H01J23/04

    摘要: A semiconductor device for electron emission in a vacuum comprises a stack of two or more semi-conductor layers of N and P type according to sequence N/(P)/N forming a juxtaposition of two head-to-tail NP junctions, in materials belonging to the III-N family, two adjacent layers forming an interface. The semiconductor materials of the layers of the stack close to the vacuum, where the electrons reach a high energy, have a band gap Eg>c/2, where c is the electron affinity of the semiconductor material, the P-type semiconductor layer being obtained partially or completely, by doping impurities of acceptor type or by piezoelectric effect to exhibit a negative fixed charge in any interface between the layers, a positive bias potential applied to the stack supplying, to a fraction of electrons circulating in the stack, the energy needed for emission in the vacuum by an emissive zone of an output layer.

    摘要翻译: 用于真空中电子发射的半导体器件包括根据序列N /(P)/ N的两个或多个N型和P型半导体层的堆叠,形成两个头对尾NP连接的并置,材料 属于III-N族,两个相邻的层形成界面。 靠近真空的堆叠层的半导体材料,其中电子达到高能量,具有带隙Eg> c / 2,其中c是半导体材料的电子亲和力,P型半导体层是 通过掺杂受体类型的杂质或通过压电效应来获得部分或完全地获得,以在层之间的任何界面中显示负的固定电荷,施加到堆叠的积极偏置电势提供给堆叠中循环的一部分电子, 需要通过输出层的发射区在真空中发射。

    Bipolar transistor with upper heterojunction collector and method for making same
    7.
    发明授权
    Bipolar transistor with upper heterojunction collector and method for making same 有权
    具有上异质结集电极的双极晶体管及其制造方法

    公开(公告)号:US06858509B2

    公开(公告)日:2005-02-22

    申请号:US10149433

    申请日:2000-12-15

    CPC分类号: H01L29/66318 H01L29/7371

    摘要: A collector-up heterojunction bipolar transistor including, stacked on a substrate, an emitter layer, a base layer, and a collector layer. In this transistor the surface area of the base-emitter junction is of smaller dimensions than the surface area of the base-collector junction. Further, the material of the base layer exhibits a sensitivity of the electrical conductivity to ion implantation that is lower than the sensitivity of the electrical conductivity of the material of the emitter layer to the same ion implantation.

    摘要翻译: 一种收集器异质结双极晶体管,包括堆叠在基板上的发射极层,基极层和集电极层。 在该晶体管中,基极 - 发射极结的表面积比基极 - 集电极结的表面积小。 此外,基层的材料表现出离子注入的电导率的灵敏度低于发射极层的材料对相同的离子注入的电导率的灵敏度。

    Large-scale integration monolithic microwave amplifier with tree-like
distributed topology
    8.
    发明授权
    Large-scale integration monolithic microwave amplifier with tree-like distributed topology 失效
    具有树状分布拓扑的大规模集成单片微波放大器

    公开(公告)号:US5689212A

    公开(公告)日:1997-11-18

    申请号:US562153

    申请日:1995-11-22

    摘要: Disclosed is a novel topology of monolithic, microwave amplifiers with high integration. This is a more compact topology, divided into a two-level or tree-like structure in which the division of the input signal is done firstly on each transistor Tij and, secondly, on each of the elementary transistors tijk of the transistors Tij. More specifically, the input line LE is divided into different basic lines li, each line li supplying lines lij distributed on either side of said lines li, a line lij then supplying a power transistor Tij. Application to microwave amplifiers.

    摘要翻译: 公开了具有高集成度的单片微波放大器的新颖拓扑。 这是一种更紧凑的拓扑,分为两级或树状结构,其中首先在每个晶体管Tij上完成输入信号的划分,其次在晶体管Tij的每个基本晶体管tijk上进行。 更具体地说,输入线LE被分成不同的基线L1,每条线路li提供分布在所述线路li的任一侧的线路lij,然后提供功率晶体管Tij的线路lij。 应用于微波放大器。

    Method for forming a bipolar transistor stabilized with electrical insulating elements
    9.
    发明授权
    Method for forming a bipolar transistor stabilized with electrical insulating elements 有权
    用电绝缘元件稳定的双极晶体管的形成方法

    公开(公告)号:US06451659B1

    公开(公告)日:2002-09-17

    申请号:US09453576

    申请日:1999-12-03

    IPC分类号: H01L21331

    摘要: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

    摘要翻译: 异质结双极晶体管类型的半导体部件在衬底上包括放置在基底上的集电极,基极和台面状发射体。 双极晶体管还包括与基极和发射极台面的侧面接触的电绝缘元件,所述元件具有与台面的宽度相同幅度的宽度,并为组件提供更大的稳定性。 此外,制造这种部件的方法特别包括通过发射极台面的构成层离子注入绝缘离子以确定电绝缘元件的步骤。

    Bipolar transistor stabilized with electrical insulating elements
    10.
    发明授权
    Bipolar transistor stabilized with electrical insulating elements 失效
    双极晶体管采用电绝缘元件稳压

    公开(公告)号:US6031255A

    公开(公告)日:2000-02-29

    申请号:US86599

    申请日:1998-05-29

    摘要: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

    摘要翻译: 异质结双极晶体管类型的半导体部件在衬底上包括放置在基底上的集电极,基极和台面状发射体。 双极晶体管还包括与基极和发射极台面的侧面接触的电绝缘元件,所述元件具有与台面的宽度相同幅度的宽度,并为组件提供更大的稳定性。 此外,制造这种部件的方法特别包括通过发射极台面的构成层离子注入绝缘离子以确定电绝缘元件的步骤。