公开(公告)号：US20060097396A1

公开(公告)日：2006-05-11

申请号：US11240645

申请日：2005-10-03

申请人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

发明人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/48

摘要： In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

摘要翻译： 在包括多层衬垫的半导体器件中，多层衬垫包括设置在半导体衬底上的第一衬底层，其具有设置在第一铜布线区域内的第一铜布线区域和第一层间绝缘区域，以及设置在第一铜布线区域上的第二衬垫层 所述第一焊盘层经由层间绝缘膜，以具有设置在所述第二铜布线区域内的第二铜布线区域和第二层间绝缘区域。 在半导体装置中，在第一和第二焊盘层中设置第一铜布线区域，第一层内绝缘区域，第二铜布线区域和第二层间绝缘区域，使得多层焊盘具有布局，其中， 当从半导体衬底的垂直上方观察多层衬垫时，用铜布线覆盖区域。

公开(公告)号：US07800227B2

公开(公告)日：2010-09-21

申请号：US11240645

申请日：2005-10-03

申请人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

发明人： Masamichi Kamiyama ,  Masashi Takase ,  Takanori Watanabe

IPC分类号： H01L23/522

CPC分类号： H01L24/05 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/45124 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/48

摘要： In a semiconductor device including a multilayer pad, the multilayer pad comprises a first pad layer provided over a semiconductor substrate to have a first copper wiring region and a first intralayer insulating region provided within the first copper wiring region, and a second pad layer provided over the first pad layer via an interlayer insulating film to have a second copper wiring region and a second intralayer insulating region provided within the second copper wiring region. In the semiconductor device, the first copper wiring region, the first intralayer insulating region, the second copper wiring region, and the second intralayer insulating region are provided in the first and second pad layers such that the multilayer pad has a layout in which all the regions are covered with the copper wiring when the multilayer pad is perspectively viewed from a perpendicularly upper direction for the semiconductor substrate.

摘要翻译： 在包括多层衬垫的半导体器件中，多层衬垫包括设置在半导体衬底上的第一衬底层，其具有设置在第一铜布线区域内的第一铜布线区域和第一层间绝缘区域，以及设置在第一铜布线区域上的第二衬垫层 所述第一焊盘层经由层间绝缘膜，以具有设置在所述第二铜布线区域内的第二铜布线区域和第二层间绝缘区域。 在半导体装置中，第一铜布线区域，第一内层绝缘区域，第二铜布线区域和第二层间绝缘区域设置在第一和第二焊盘层中，使得多层焊盘具有布局，其中， 当从半导体衬底的垂直上方观察多层衬垫时，用铜布线覆盖区域。

公开(公告)号：US07673266B2

公开(公告)日：2010-03-02

申请号：US11604379

申请日：2006-11-27

申请人： Masamichi Kamiyama ,  Tomoharu Awaya

发明人： Masamichi Kamiyama ,  Tomoharu Awaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function σ of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient σ, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function σ of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

摘要翻译： 定时分析方法评价要设计的目标电路的性能，并且包括基于包括形成目标的宏小区的布置的布局信息来计算耦合并形成目标电路的两个任意宏小区之间的相关系数r 电路和相关信息，指示与宏小区对的每个布置相耦合的两个宏小区之间的相关性，计算分布函数＆sgr; 基于相关系数＆sgr，两个任意宏小区的延迟时间的标准偏差;以及基于相关系数r和分布函数＆sgr执行目标电路的统计时序分析; 相对于形成目标电路的每个宏单元对的标准偏差。

公开(公告)号：US20070220467A1

公开(公告)日：2007-09-20

申请号：US11604379

申请日：2006-11-27

申请人： Masamichi Kamiyama ,  Tomoharu Awaya

发明人： Masamichi Kamiyama ,  Tomoharu Awaya

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function σ of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient σ, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function σ of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

摘要翻译： 定时分析方法评价要设计的目标电路的性能，并且包括基于包括形成目标的宏小区的布置的布局信息来计算耦合并形成目标电路的两个任意宏小区之间的相关系数r 电路和相关信息，其指示与宏小区对的每个布置耦合的两个宏小区之间的相关性，基于相关系数sigma计算两个任意宏小区的延迟时间的标准偏差的分布函数sigma，并携带 基于相关系数r和相对于形成目标电路的每个宏小区对的标准偏差的分布函数sigma，对目标电路进行统计时序分析。

公开(公告)号：US5754061A

公开(公告)日：1998-05-19

申请号：US718015

申请日：1996-09-03

申请人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

发明人： Shinzou Satou ,  Kou Ebihara ,  Akiyoshi Suzuki ,  Keisuke Ishiwata ,  Kouji Miki ,  Hitoshi Ohmichi ,  Tamio Miyamura ,  Masamichi Kamiyama

IPC分类号： H03K19/08 ,  H03K19/00 ,  H03K19/003 ,  H03K19/013 ,  H03K19/02 ,  H03K17/04

CPC分类号： H03K19/00353 ,  H03K19/001 ,  H03K19/0136

摘要： A Bi-CMOS circuit includes a first bipolar, a second bipolar transistor and a CMOS control unit for performing switching controls of the first and second bipolar transistors on the basis of an input signal applied to an input terminal and for controlling an output signal output via the output terminal on the basis of the input signal. A turn-OFF unit temporality couples the base of the first bipolar transistor to a low-potential side power supply line on the basis of a current flowing in said control means when the first bipolar transistor is turned OFF, so that the first bipolar transistor can be rapidly turned OFF.

摘要翻译： 一种双CMOS电路包括第一双极型，第二双极晶体管和CMOS控制单元，用于根据施加到输入端的输入信号执行第一和第二双极晶体管的开关控制，并用于控制输出信号经由 输出端基于输入信号。 基于在第一双极晶体管截止时流过所述控制装置的电流，关断单元暂时性将第一双极晶体管的基极连接到低电位侧电源线，使得第一双极晶体管可 快速关闭。