公开(公告)号：US07135398B2

公开(公告)日：2006-11-14

申请号：US10901868

申请日：2004-07-29

申请人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

发明人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

摘要翻译： 公开了一种具有混合电介质的高级后端（BEOL）互连结构。 用于通孔电平的层间电介质（ILD）优选地不同于线路电平的ILD。 在优选实施例中，通孔级ILD由低k SiCOH材料形成，并且线级ILD由低k聚合物热固性材料形成。

公开(公告)号：US06917108B2

公开(公告)日：2005-07-12

申请号：US10294139

申请日：2002-11-14

申请人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

发明人： John A. Fitzsimmons ,  Stephen E. Greco ,  Jia Lee ,  Stephen M. Gates ,  Terry Spooner ,  Matthew S. Angyal ,  Habib Hichri ,  Theordorus E. Standaert ,  Glenn A. Biery

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An advanced back-end-of-line (BEOL) interconnect structure having a hybrid dielectric is disclosed. The inter-layer dielectric (ILD) for the via level is preferably different from the ILD for the line level. In a preferred embodiment, the via-level ILD is formed of a low-k SiCOH material, and the line-level ILD is formed of a low-k polymeric thermoset material.

公开(公告)号：US06734096B2

公开(公告)日：2004-05-11

申请号：US10053288

申请日：2002-01-17

申请人： Timothy J. Dalton ,  Minakshisundaran B. Anand ,  Michael D. Armacost ,  Shyng-Tsong Chen ,  Stephen M. Gates ,  Stephen E. Greco ,  Simon M. Karecki ,  Satyanarayana V. Nitta

发明人： Timothy J. Dalton ,  Minakshisundaran B. Anand ,  Michael D. Armacost ,  Shyng-Tsong Chen ,  Stephen M. Gates ,  Stephen E. Greco ,  Simon M. Karecki ,  Satyanarayana V. Nitta

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  H01L21/76811 ,  H01L21/76826

摘要： A method is described for forming a metal pattern in a low-dielectric constant substrate. A hardmask is prepared which includes a low-k lower hardmask layer and a top hardmask layer. The top hardmask layer is a sacrificial layer with a thickness of about 200 Å, preferably formed of a refractory nitride, and which serves as a stopping layer in a subsequent CMP metal removal process. The patterning is performed using resist layers. Oxidation damage to the lower hardmask layer is avoided by forming a protective layer in the hardmask, or by using a non-oxidizing resist strip process.

摘要翻译： 描述了在低介电常数衬底中形成金属图案的方法。 准备了一个硬掩模，其包括低k较低的硬掩模层和顶部硬掩模层。 顶部硬掩模层是厚度为约200埃的牺牲层，优选由耐火氮化物形成，并且在随后的CMP金属去除工艺中用作停止层。 使用抗蚀剂层进行图案化。 通过在硬掩模中形成保护层，或者通过使用非氧化抗蚀剂剥离工艺来避免对下部硬掩模层的氧化损伤。

公开(公告)号：US08492268B2

公开(公告)日：2013-07-23

申请号：US13410466

申请日：2012-03-02

申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

IPC分类号： H01L23/52

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

公开(公告)号：US08484586B2

公开(公告)日：2013-07-09

申请号：US13517811

申请日：2012-06-14

申请人： Timothy A. Brunner ,  Stephen E. Greco ,  Bernhard R. Liegl ,  Hua Xiang

发明人： Timothy A. Brunner ,  Stephen E. Greco ,  Bernhard R. Liegl ,  Hua Xiang

IPC分类号： G06F17/50 ,  G02B7/04 ,  H01L27/00

CPC分类号： G06F17/5045 ,  G03F1/144 ,  G03F1/36 ,  G03F1/70 ,  G03F7/705

摘要： A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

公开(公告)号：US20120164758A1

公开(公告)日：2012-06-28

申请号：US13410466

申请日：2012-03-02

申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

IPC分类号： H01L21/66

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。

公开(公告)号：US07439173B2

公开(公告)日：2008-10-21

申请号：US11869044

申请日：2007-10-09

申请人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

发明人： Stephen E. Greco ,  Chao-Kun Hu ,  Paul S. McLaughlin

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.

摘要翻译： 公开了一种具有增加的电迁移寿命和允许电流密度的集成电路及其形成方法。 在一个实施例中，集成电路包括连接到至少一个功能通孔的导线，以及至少一个虚拟通孔，其具有与导电线电连接的第一下端，以及电连接（隔离）至任何导电 线。 每个虚拟通孔从导电线垂直向上延伸，并且去除快速扩散路径的一部分，即金属到电介质盖界面，其被金属对金属衬垫界面代替。 因此，每个虚拟通孔可以减少金属扩散速率，从而增加电迁移寿命并允许增加电流密度。

公开(公告)号：US06479884B2

公开(公告)日：2002-11-12

申请号：US09893786

申请日：2001-06-29

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L2358

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

摘要翻译： 抗蚀剂显影剂可以攻击一些先进的介电材料，例如可以用作集成电路芯片的表面和形成在介电材料表面上的布线层之间的绝缘体的倍半硅氧烷材料。 通过进行抗蚀剂剥离或蚀刻工艺，其中将反应物材料从电介质材料外部供应或释放出来，可以形成非常薄的中间材料的表面保护覆盖层，其不能抵抗显影剂或多种其它材料 这可能会损坏可流动的氧化物材料。 因此，与芯片形成牢固的连接和通孔的双镶嵌工艺可以与具有特别低介电常数的先进电介质相兼容，以最小化导体电容并支持快速的信号传播和抗噪声性，即使导体彼此间隔紧密。

公开(公告)号：US06329280B1

公开(公告)日：2001-12-11

申请号：US09311470

申请日：1999-05-13

申请人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

发明人： Robert Cook ,  Stephen E. Greco ,  John P. Hummel ,  Joyce Liu ,  Vincent J. McGahay ,  Rebecca Mih ,  Kamalesh Srivastava

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L2221/1063

摘要： Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

公开(公告)号：US08299622B2

公开(公告)日：2012-10-30

申请号：US12186061

申请日：2008-08-05

申请人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

发明人： Dureseti Chidambarrao ,  Stephen E. Greco ,  Kia S. Low

IPC分类号： H01L23/52

CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An IC including first metal layer having wiring running in a first direction; a second metal layer having wiring running in a second direction perpendicular to the first direction; and a first via layer between the first metal layer and the second metal layer, the first via layer including a viabar interconnecting the first metal layer to the second metal layer at a first location where the first metal layer vertically coincides with the second metal layer and, at a second location, connecting to wiring of the first metal layer but not wiring of the second metal layer.

摘要翻译： 一种IC，包括具有在第一方向上延伸的布线的第一金属层; 具有沿与第一方向垂直的第二方向延伸的布线的第二金属层; 以及在所述第一金属层和所述第二金属层之间的第一通孔层，所述第一通孔层包括在所述第一金属层与所述第二金属层垂直重合的第一位置处将所述第一金属层与所述第二金属层互连的viabar， 在第二位置处连接到第一金属层的布线而不是第二金属层的布线。