公开(公告)号：US06717217B2

公开(公告)日：2004-04-06

申请号：US10341819

申请日：2003-01-14

申请人： Keith E. Fogel ,  Maurice H. Norcott ,  Devendra K. Sadana

发明人： Keith E. Fogel ,  Maurice H. Norcott ,  Devendra K. Sadana

IPC分类号： H01L2176

CPC分类号： H01L21/76243

摘要： A method of forming a silicon-on-insulator (SOI) substrate having a buried oxide region that has a greater content of thermally grown oxide as compared to oxide formed by implanted oxygen ions is provided. Specifically, the inventive SOI substrate is formed by utilizing a method wherein oxygen ions are implanted into a surface of a Si-containing substrate that includes a sufficient Si thickness to allow for subsequent formation of a buried oxide region in the Si-containing substrate which has a greater content of thermally grown oxide as compared to oxide formed by the implanted oxygen ions followed by an annealing step. The sufficient Si thickness can be obtained by (i) forming a Si layer on the surface of the implanted substrate prior to annealing; (ii) conducting a high-energy, high-dose oxygen implant to ensure that the oxygen ions are implanted a sufficient distance from the surface of the Si-containing substrate; or (iii) conducting a high-energy, low-dose oxygen implant so that less implanted oxide is present in the Si-containing substrate.

摘要翻译： 提供了一种形成具有与由植入的氧离子形成的氧化物相比具有更大含量的热生长氧化物的掩埋氧化物区域的绝缘体上硅（SOI）衬底的方法。 具体地说，本发明的SOI衬底是通过利用其中将氧离子注入包含足够的Si厚度的含Si衬底的表面中以允许随后在含Si衬底中形成掩埋氧化物区域的方法形成的， 与由注入的氧离子形成的氧化物相比，随后进行退火步骤，热生长氧化物的含量更高。 可以通过（i）在退火之前在注入的衬底的表面上形成Si层来获得足够的Si厚度; （ii）进行高能量高剂量氧注入，以确保从含Si衬底表面注入足够距离的氧离子; 或（iii）进行高能量，低剂量的氧注入，使得在含Si衬底中存在少量注入的氧化物。

公开(公告)号：US5371654A

公开(公告)日：1994-12-06

申请号：US963346

申请日：1992-10-19

申请人： Brian S. Beaman ,  Fuad E. Doany ,  Keith E. Fogel ,  James L. Hedrick, Jr. ,  Paul A. Lauro ,  Maurice H. Norcott ,  John J. Ritsko ,  Leathen Shi ,  Da-Yuan Shih ,  George F. Walker

发明人： Brian S. Beaman ,  Fuad E. Doany ,  Keith E. Fogel ,  James L. Hedrick, Jr. ,  Paul A. Lauro ,  Maurice H. Norcott ,  John J. Ritsko ,  Leathen Shi ,  Da-Yuan Shih ,  George F. Walker

IPC分类号： H01L23/52 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K7/00

CPC分类号： G01R1/07371 ,  G01R1/07307 ,  G01R1/07314 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/2886 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0652 ,  G01R1/06711 ,  G01R1/0675 ,  G01R1/07378 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1627 ,  H01L2924/19107 ,  H01L2924/3011 ,  Y10S29/029 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49158 ,  Y10T29/49162 ,  Y10T29/49192 ,  Y10T29/53174

摘要： The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection electrically interconnecting each assembly. The electrical interconnection formed from an elastomeric interposer having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection is disposed over the array of electronic devices so that the electrical interconnection between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection between adjacent assemblies. Methods for fabricating the electrical interconnection as a stand alone elastomeric sheet are described.

摘要翻译： 本发明涉及用于将三维结构中的诸如半导体芯片的电子器件封装在一起的结构，其允许电信号水平和垂直地传播。 该结构由多个组件形成。 每个组件由在多个电子装置的至少一个表面上设置的基板形成。 每个组件设置在相邻组件的堆叠中。 在相邻组件之间存在电互连，每个组件电连接。 由具有延伸穿过其中的多个孔的弹性体插入件形成的电互连。 孔阵列对应于基片上的电子器件阵列。 孔和电互连布置在电子器件阵列上，使得相邻电子器件之间的电互连。 组合堆叠被压缩，从而压缩相邻组件之间的电互连。 描述了用于制造作为独立弹性片的电互连的方法。

公开(公告)号：US5635846A

公开(公告)日：1997-06-03

申请号：US55485

申请日：1993-04-30

申请人： Brian S. Beaman ,  Keith E. Fogel ,  Paul A. Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George F. Walker

发明人： Brian S. Beaman ,  Keith E. Fogel ,  Paul A. Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George F. Walker

IPC分类号： H01L23/52 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G01R31/02

CPC分类号： G01R1/07371 ,  G01R1/07307 ,  G01R1/07314 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/2886 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0652 ,  G01R1/06711 ,  G01R1/0675 ,  G01R1/07378 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1627 ,  H01L2924/19107 ,  H01L2924/3011 ,  Y10S29/029 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49158 ,  Y10T29/49162 ,  Y10T29/49192 ,  Y10T29/53174

摘要： A high density test probe is for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

摘要翻译： 高密度测试探头用于测试晶圆形式的高密度和高性能集成电路或分立芯片。 测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。 使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。 电线被连接到空间变压器表面上的接触焊盘阵列。 空间变压器由多层集成电路芯片封装基板形成。 电线与接触位置阵列一样密集。 围绕着向外突出的线的阵列设置模具。 液体弹性体设置在模具中以填充电线之间的空间。 弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上， 其中细长导体被接合。 这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。 或者，插入器电连接器可以设置在第一和第二空间变压器之间。

公开(公告)号：US07276919B1

公开(公告)日：2007-10-02

申请号：US08756830

申请日：1996-11-20

申请人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

发明人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

IPC分类号： G01R31/06

CPC分类号： G01R1/07314 ,  G01R1/06761 ,  G01R1/0735

摘要： A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.

摘要翻译： 描述了高密度集成测试探针和制造方法。 将一组电线球焊接到扇形外壳的表面上的接触位置。 电线被剪断，留下一个短截线，其末端被砧平坦化。 在平坦化具有一组孔的材料的片材之前，布置成使一组短截线对准，以便将短截线组放置在短截线上。 该材料片支撑放大的尖端。 具有短截线的基底形成探针，该探针移动成与诸如滴液或包装基底的工件上的接触位置接合。

公开(公告)号：US06756639B2

公开(公告)日：2004-06-29

申请号：US10185580

申请日：2002-06-28

申请人： Maurice H. Norcott ,  Devendra K. Sadana

发明人： Maurice H. Norcott ,  Devendra K. Sadana

IPC分类号： H01L2900

CPC分类号： H01L21/76243 ,  H01L21/26533

摘要： A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

摘要翻译： 利用氧离子注入步骤在半导体衬底中制造缺陷诱导的掩埋氧化物（DIBOX）区域以产生稳定的缺陷区域的方法; 低能量注入步骤，以产生与所述稳定缺陷区相邻的非晶层，其中所述低能量注入步骤使用除氧以外的至少一种离子; 提供氧化和任选的退火。 本文还提供了包含具有图案化或未图案化形式的DIBOX区域的半导体衬底的绝缘体上硅（SOI）材料。

公开(公告)号：US06486037B2

公开(公告)日：2002-11-26

申请号：US09861593

申请日：2001-05-21

申请人： Maurice H. Norcott ,  Devendra K. Sadana

发明人： Maurice H. Norcott ,  Devendra K. Sadana

IPC分类号： H02L21265

CPC分类号： H01L21/76243 ,  H01L21/26533

摘要： A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

摘要翻译： 利用氧离子注入步骤在半导体衬底中制造缺陷诱导的掩埋氧化物（DIBOX）区域以产生稳定的缺陷区域的方法; 低能量注入步骤，以产生与所述稳定缺陷区相邻的非晶层，其中所述低能量注入步骤使用除氧以外的至少一种离子; 提供氧化和任选的退火。 本文还提供了包含具有图案化或未图案化形式的DIBOX区域的半导体衬底的绝缘体上硅（SOI）材料。

公开(公告)号：US06541356B2

公开(公告)日：2003-04-01

申请号：US09861596

申请日：2001-05-21

申请人： Keith E. Fogel ,  Maurice H. Norcott ,  Devendra K. Sadana

发明人： Keith E. Fogel ,  Maurice H. Norcott ,  Devendra K. Sadana

IPC分类号： H01L2131

CPC分类号： H01L21/76243

摘要： A method of forming a silicon-on-insulator (SOI) substrate having a buried oxide region that has a greater content of thermally grown oxide as compared to oxide formed by implanted oxygen ions is provided. Specifically, the inventive SOI substrate is formed by utilizing a method wherein oxygen ions are implanted into a surface of a Si-containing substrate that includes a sufficient Si thickness to allow for subsequent formation of a buried oxide region in the Si-containing substrate which has a greater content of thermally grown oxide as compared to oxide formed by the implanted oxygen ions followed by an annealing step. The sufficient Si thickness can be obtained by (i) forming a Si layer on the surface of the implanted substrate prior to annealing; (ii) conducting a high-energy, high-dose oxygen implant to ensure that the oxygen ions are implanted a sufficient distance from the surface of the Si-containing substrate; or (iii) conducting a high-energy, low-dose oxygen implant so that less implanted oxide is present in the Si-containing substrate.

公开(公告)号：US06332270B2

公开(公告)日：2001-12-25

申请号：US09198179

申请日：1998-11-23

申请人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

发明人： Brian Samuel Beaman ,  Keith Edward Fogel ,  Paul Alfred Lauro ,  Maurice H. Norcott ,  Da-Yuan Shih ,  George Frederick Walker

IPC分类号： H01R914

CPC分类号： G01R1/07378 ,  G01R1/07314 ,  G01R3/00 ,  H01L2224/16225 ,  H01L2924/15312 ,  Y10T29/49004 ,  Y10T29/49151 ,  Y10T29/49222

摘要： A high density integrated test probe and method of fabrication is described. A group of wires are ball bonded to contact locations on the surface of a fan out substrate. The wires are sheared off leaving a stub, the end of which is flattened by an anvil. Before flattening a sheet of material having a group of holes is arranged for alignment with the group of stubs is disposed over the stubs. The sheet of material supports the enlarged tip. The substrate with stubs form a probe which is moved into engagement with contact locations on a work piece such as a drip or packaging substrate.

摘要翻译： 描述了高密度集成测试探针和制造方法。 将一组电线球焊接到扇形外壳的表面上的接触位置。 电线被剪断，留下一个短截线，其末端被砧平坦化。 在平坦化具有一组孔的材料的片材之前，布置成使一组短截线对准，以便将短截线组放置在短截线上。 该材料片支撑放大的尖端。 具有短截线的基底形成探针，该探针移动成与诸如滴液或包装基底的工件上的接触位置接合。

公开(公告)号：US5531022A

公开(公告)日：1996-07-02

申请号：US300620

申请日：1994-09-02

申请人： Brain S. Beaman ,  Fuad E. Doany ,  Keith E. Fogel ,  James L. Hedrick, Jr. ,  Paul A. Lauro ,  Maurice H. Norcott ,  John J. Ritsko ,  Leathen Shi ,  Da-Yuan Shih ,  George F. Walker

发明人： Brain S. Beaman ,  Fuad E. Doany ,  Keith E. Fogel ,  James L. Hedrick, Jr. ,  Paul A. Lauro ,  Maurice H. Norcott ,  John J. Ritsko ,  Leathen Shi ,  Da-Yuan Shih ,  George F. Walker

IPC分类号： H01L23/52 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H05K3/40 ,  H01R9/09

CPC分类号： G01R1/07371 ,  G01R1/07307 ,  G01R1/07314 ,  G01R1/07342 ,  G01R3/00 ,  G01R31/2886 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/0652 ,  G01R1/06711 ,  G01R1/0675 ,  G01R1/07378 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/1627 ,  H01L2924/19107 ,  H01L2924/3011 ,  Y10S29/029 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49158 ,  Y10T29/49162 ,  Y10T29/49192 ,  Y10T29/53174

摘要： The present invention is directed to a structure for packaging electronic devices, such as semiconductor chips, in a three dimensional structure which permits electrical signals to propagate both horizontally and vertically. The structure is formed from a plurality of assemblies. Each assembly is formed from a substrate having disposed on at least one surface a plurality of electronic devices. Each assembly is disposed in a stack of adjacent assemblies. Between adjacent assemblies there is an electrical interconnection means electrically interconnecting each assembly. The electrical interconnection means is formed from an elastomeric interposer. The elastomeric interposer is formed from an elastomeric material having a plurality of electrical conductors extending therethrough, either in a clustered or un-clustered arrangement. The electrical interconnection means is fabricated having a plurality of apertures extending therethrough. The array of apertures corresponds to the array of electronic devices on the substrates. The aperture and electrical interconnection means is disposed over the array of electronic devices so that the electrical interconnection means is between adjacent electronic devices. The stack of assemblies is compressed thereby compressing the electrical interconnection means between adjacent assemblies. The substrate or each assembly is formed from a thermally conductive material such as diamond. A heat dissipation means is thermally connected to the edges of the substrate to extract heat generated within the structure. Methods for fabricating the electrical interconnection means as a stand alone elastomeric sheet are described. The ends of the plurality of conductors in the electrical interconnection means are fabricated so that upon compression between adjacent assemblies there is a wiping action between the conductor ends and contact locations on the adjacent assemblies to form a good electrical contact therewith.