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    Method of making a high performance, small area thin film transistor
    1.
    发明授权
    Method of making a high performance, small area thin film transistor 失效
    制造高性能，小面积薄膜晶体管的方法

    公开(公告)号：US4543320A

    公开(公告)日：1985-09-24

    申请号：US549991

    申请日：1983-11-08

    Applicant: Meera Vijan

    Inventor： Meera Vijan

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/336 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  G03C5/00

    CPC classification number: H01L29/6675 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/78642

    Abstract: A method of making a high performance, small area thin film transistor having a drain region, an insulating layer, and a source region forming a non-coplanar surface with respect to a substrate is disclosed. The insulative layer is formed in between the source and drain regions. A deposited semiconductor overlies the non-coplanar surface to form a current conduction channel between the drain and source. A gate insulator and gate electrode overly at least a portion of the deposited semiconductor adjacent thereto. The non-coplanar surface can be formed by utilizing a dry process to simultaneously etch through several layers in a continuous one-step process. A second dielectric layer may be formed above the three previous layers. This decouples the gate electrode from the source region by creating two capacitances in series, thereby limiting the capacitance between the gate electrode and the source region.

    Abstract translation: 公开了一种制造具有漏极区，绝缘层和形成相对于衬底的非共面的源极区的高性能小面积薄膜晶体管的方法。 绝缘层形成在源区和漏区之间。 沉积的半导体覆盖非共面表面以在漏极和源极之间形成电流传导沟道。 栅极绝缘体和栅电极超过与其相邻的沉积半导体的至少一部分。 可以通过利用干法在连续的一步法中同时蚀刻几层来形成非共面表面。 可以在三个先前层之上形成第二介电层。 这通过产生串联的两个电容来将栅电极与源极区分开，从而限制栅电极和源极区之间的电容。

    Combination of photovoltaic devices and batteries which utilize a solid polymeric electrolyte
    3.
    发明申请
    Combination of photovoltaic devices and batteries which utilize a solid polymeric electrolyte 审中-公开
    使用固体聚合物电解质的光伏器件和电池的组合

    公开(公告)号：US20070054158A1

    公开(公告)日：2007-03-08

    申请号：US11328531

    申请日：2006-01-10

    Applicant: Stanford Ovshinsky ,  Boyko Aladjov ,  Meera Vijan

    Inventor： Stanford Ovshinsky ,  Boyko Aladjov ,  Meera Vijan

    IPC: H01M16/00 ,  H01M4/48 ,  H01M4/52 ,  H01L31/00

    CPC classification number: H01M10/347 ,  H01L31/03762 ,  H01M4/242 ,  H01M4/32 ,  H01M4/36 ,  H01M4/383 ,  H01M4/48 ,  H01M4/50 ,  H01M4/52 ,  H01M4/5825 ,  H01M4/60 ,  H01M10/0565 ,  H01M10/30 ,  H01M10/36 ,  H01M10/465 ,  H01M16/00 ,  H01M16/003 ,  H01M2300/0082 ,  H02S20/25 ,  H02S40/38 ,  Y02E60/124

    Abstract: A combination of photovoltaic devices and solid state batteries. The solid state battery comprising at least one negative electrode which may include a metal hydride active material, at least one positive electrode including an active material, and an anionic exchange membrane disposed between said negative electrode and said positive electrode. The anionic exchange membrane may be selected from materials allowing the flow of hydroxyl ions therethrough while simultaneously electrically separating the positive and negative electrodes. The anionic exchange membrane may be selected from a number of different materials based on different chemistries which allow the flow of hydroxyl ions therethrough. The anionic exchange membrane may be comprised of a polystyrene-divinylbenzene-polyvinylchloride polymeric material. The photovoltaic devices may be amorphous silicon solar cells. The photovoltaic devices may be triple junction, tandem amorphous silicon solar cells. The photovoltaic devices may be in the form of a roofing material. The photovoltaic devices may be deposited on thin film plastic material such as Kapton.

    Abstract translation: 光伏器件和固态电池的组合。 所述固态电池包括至少一个负极，所述负电极可包括金属氢化物活性材料，至少一种包括活性材料的正电极和设置在所述负电极和所述正电极之间的阴离子交换膜。 阴离子交换膜可以选自允许羟基离子流过其中的材料，同时电分离正极和负极。 阴离子交换膜可以选自许多基于允许羟基离子流过其中的不同化学物质的不同材料。 阴离子交换膜可以由聚苯乙烯 - 二乙烯基苯 - 聚氯乙烯聚合物材料组成。 光伏器件可以是非晶硅太阳能电池。 光伏器件可以是三结，串联非晶硅太阳能电池。 光伏器件可以是屋顶材料的形式。 光伏器件可以沉积在诸如Kapton的薄膜塑料材料上。

    Method of forming a large surface area integrated circuit
    8.
    发明授权
    Method of forming a large surface area integrated circuit 失效
    形成大面积集成电路的方法

    公开(公告)号：US4696885A

    公开(公告)日：1987-09-29

    申请号：US861756

    申请日：1986-05-09

    Applicant: Meera Vijan

    Inventor： Meera Vijan

    IPC: G03F7/16 ,  H05K1/00 ,  H05K3/00 ,  H01L21/312

    CPC classification number: G03F7/16 ,  H05K1/0393 ,  H05K3/0091 ,  H05K3/0097 ,  Y10S430/136

    Abstract: A method of forming a large area electronic element, e.g., a large area integrated microelectronic circuit which has at least one dimension in excess of three inches, by forming a film of photoresist separate from a surface to be etched, and thereafter depositing the film of photoresist on the surface to be etched. The deposited photoresist film is then exposed to actinic radiation and developed, and the exposed, underlying surface may thereafter be etched.The method for depositing the photoresist involves passing a viscous liquid composed of photoresist and solvent under positive pressure through a very thin elongated orifice that extends across and in close proximity to (e.g., 0.01 inch or less), but spaced apart from the surface to be processed to form a very thin flexible continuous film of liquid photoresist composition issuing from the orifice. The surface to be processed is linearly moved past the orifice so as to deposit the issued film of photoresist on the surface, in a thickness no greater than 100 microns, and preferably much less. The wet deposited film is then heated to drive off the solvent thereby reducing the thickness of the photoresist. The method disclosed herein is particularly suitable for processing large area rectangular substrates and continuous flexible substrates used in roll-to-roll processing equipment.

    Abstract translation: 通过形成与要蚀刻的表面分离的光致抗蚀剂膜，形成大面积电子元件的方法，例如具有至少一个尺寸超过三英寸的大面积集成微电子电路，然后将 要蚀刻的表面上的光致抗蚀剂。 然后将沉积的光致抗蚀剂膜暴露于光化辐射并显影，然后暴露的下面的表面可以被蚀刻。 沉积光致抗蚀剂的方法包括将由光致抗蚀剂和溶剂组成的粘性液体在正压下通过非常薄的细长孔，其延伸越过（例如，0.01英寸或更小），但距表面间隔开 加工成形成从孔口发出的液体光致抗蚀剂组合物的非常薄的柔性连续膜。 要处理的表面线性地移动通过孔口，以便在表面上沉积所发布的光致抗蚀剂膜，厚度不大于100微米，优选少得多。 然后将湿沉积膜加热以驱除溶剂，从而减小光致抗蚀剂的厚度。 本文公开的方法特别适用于处理卷对卷加工设备中使用的大面积矩形基板和连续柔性基板。

    Method of forming thin film semiconductor devices
    9.
    发明授权
    Method of forming thin film semiconductor devices 失效
    薄膜半导体器件的形成方法

    公开(公告)号：US4680085A

    公开(公告)日：1987-07-14

    申请号：US851756

    申请日：1986-04-14

    Applicant: Meera Vijan ,  John C. McGill ,  Paul N. Day

    Inventor： Meera Vijan ,  John C. McGill ,  Paul N. Day

    IPC: H01L21/3213 ,  H01L21/77 ,  H01L21/84 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C23F1/02

    CPC classification number: H01L21/32137 ,  H01L27/1214 ,  Y10S438/963

    Abstract: Thin film semiconductor devices such as amorphous silicon alloy p-i-n diodes and the like which utilize mesa-like semiconductor structures having vertical sidewalls are formed by a process which eliminates overhangs and neutralizes contaminants on the sidewalls that can result in short circuits or degradation of device performance. Smooth vertical sidewalls free of overhangs and voids are created by: successively depositing the desired semiconductor layers on a substrate, then depositing and patterning a top metal contact mask on the semiconductor layers, followed by removing the unwanted portions of the semiconductor layers by reactive ion etching. The disclosed reactive ion etching provides controlled vertical etching with virtually no lateral etching, thereby providing smooth sidewalls. The top metal contact mask protects the underlying semiconductor layers during the anisotropic etching process, and its edges are precisely aligned with the sidewalls of the underlying semiconductor layers that define the mesa structure when the etching is complete. The top metal contact mask which is formed by conventional deposition and patterning techniques, serves as a connection between the metal electrode which connects semiconductor layers of the mesa structure to the top metallization which is patterned to define desired interconnections. Ion damage and contaminants formed on the sidewalls during etching are removed or neutralized by contacting the sidewalls with a base solution and/or annealing the mesa structure before it is covered with an insulation layer.

    Abstract translation: 利用具有垂直侧壁的台面状半导体结构的诸如非晶硅合金p-i-n二极管等的薄膜半导体器件通过消除悬垂并中和侧壁上的污染物的过程形成，这可能导致器件性能的短路或劣化。 没有突出端和空隙的平滑垂直侧壁通过以下方式产生：依次在衬底上沉积所需的半导体层，然后在半导体层上沉积和图案化顶部金属接触掩模，然后通过反应离子蚀刻去除半导体层的不希望的部分 。 所公开的反应离子蚀刻提供受控的垂直蚀刻，实际上没有横向蚀刻，从而提供平滑的侧壁。 顶部金属接触掩模在各向异性蚀刻工艺期间保护下面的半导体层，并且当蚀刻完成时，其边缘与限定台面结构的下面的半导体层的侧壁精确对准。 通过常规沉积和图案化技术形成的顶部金属接触掩模用作将台面结构的半导体层与顶部金属化连接的金属电极之间的连接，其被图案化以限定所需的互连。 在蚀刻期间在侧壁上形成的离子损伤和污染通过使侧壁与基底溶液接触和/或在其被绝缘层覆盖之前退火台面结构而被去除或中和。

    High current thin film transistor
    10.
    发明授权
    High current thin film transistor 失效
    大电流薄膜晶体管

    公开(公告)号：US4547789A

    公开(公告)日：1985-10-15

    申请号：US549978

    申请日：1983-11-08

    Applicant: Vincent D. Cannella ,  Gregory L. Hansell ,  Zvi Yaniv ,  Meera Vijan

    Inventor： Vincent D. Cannella ,  Gregory L. Hansell ,  Zvi Yaniv ,  Meera Vijan

    IPC: H01L29/04 ,  H01L29/786 ,  H01L29/78

    CPC classification number: H01L29/78642 ,  H01L29/04 ,  H01L29/78684

    Abstract: A new and improved thin film field effect transistor has increased operating current and speed. The transistor includes a drain, an insulator, and a source formed in layers and vertically arranged with respect to a substrate and each other. The drain, however, and source layers form a plurality of non-coplanar surfaces with respect to the substrate. The device further includes a deposited semiconductor material overlying the non-coplanar surfaces to form a plurality of current conduction channels between the drain and source. A gate insulator overlies the semiconductor material, and a gate electrode overlies the gate insulator. The devices can also include carrier injection structure including a doped semiconductor material electrically coupled to the drain, the source, and the deposited semiconductor material for increasing the injection of current conduction carriers in the current conduction channels.

    Abstract translation: 新的改进的薄膜场效应晶体管具有增加的工作电流和速度。 晶体管包括漏极，绝缘体和源层，并相对于衬底彼此垂直布置。 然而，漏极和源极层相对于衬底形成多个非共面表面。 该器件还包括覆盖非共面表面的沉积半导体材料，以在漏极和源极之间形成多个电流传导通道。 栅极绝缘体覆盖半导体材料，并且栅极电极覆盖栅极绝缘体。 器件还可以包括载流子注入结构，其包括电耦合到漏极，源极和沉积的半导体材料的掺杂半导体材料，用于增加电流传导沟道中的电流传导载流子的注入。

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