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公开(公告)号：US5659609A
公开(公告)日：1997-08-19
申请号：US503620
申请日：1995-07-18
Applicant: Nobukazu Koizumi , Mitsuo Kakuishi , Yutaka Awata
Inventor： Nobukazu Koizumi , Mitsuo Kakuishi , Yutaka Awata
CPC classification number: H04B3/23
Abstract: An echo canceller is disclosed which generates an echo replica based on a transmit signal to cancel an echo. The echo canceller includes a linear echo canceller circuit for generating an echo replica of the transmit signal in the absence of distortion. The echo canceller further includes a waveform-distortion compensation circuit, coupled with the linear echo canceller circuit, for generating an echo replica for compensating waveform distortion occurred in an echo response when the transmit signal is distorted. In the echo canceller, the echo is canceled by use of the echo replica generated in the linear echo canceller circuit in the absence of distortion in the transmit signal, and is canceled by use of the echo replica generated in the waveform-distortion compensation circuit when the transmit signal is distorted.
Abstract translation: 公开了一种回波消除器，其基于发送信号产生回波复制以消除回波。 回波消除器包括用于在不存在失真的情况下产生发射信号的回波复制品的线性回波消除器电路。 回波消除器还包括与线性回波消除器电路耦合的波形失真补偿电路，用于产生用于在发送信号失真时在回波响应中发生的波形失真的回波复制品。 在回波消除器中，通过在发送信号中没有失真的情况下，通过使用在线性回波消除器电路中生成的回波副本来消除回波，并且通过使用在波形失真补偿电路中产生的回波复制来解除回波 发送信号失真。
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公开(公告)号：US5471507A
公开(公告)日：1995-11-28
申请号：US122500
申请日：1993-09-28
Applicant: Yutaka Awata , Mitsuo Kakuishi
Inventor： Yutaka Awata , Mitsuo Kakuishi
CPC classification number: H04Q1/50 , G06F1/32 , H04Q1/30 , H04L2007/047
Abstract: An input analog signal having a periodicity is converted into one-bit digital signals by an A/D converter (42), and the one-bit digital signals are converted into parallel signals by a serial-to-parallel converter (43). A correlation between the parallel signals and a reference signal string is detected by a correlation device (45). When the correlation is detected, a hold circuit (48) holds detection of the correlation and hence outputs a tone signal detection result. With the above simple, low power consumption circuit structure, the tone signal can be detected.
Abstract translation: PCT No.PCT / JP93 / 00100 Sec。 371日期：1993年9月28日 102（e）日期1993年9月28日PCT 1993年1月28日PCT公布。 公开号WO93 / 15580 日期：1993年5月8日。具有周期性的输入模拟信号由A / D转换器（42）转换成1位数字信号，一位数字信号通过串行到并行转换成并行信号 转换器（43）。 相关装置（45）检测并行信号和参考信号串之间的相关性。 当检测到相关时，保持电路（48）保持相关的检测，从而输出音调信号检测结果。 利用上述简单的低功耗电路结构，可以检测音调信号。
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公开(公告)号：US5151937A
公开(公告)日：1992-09-29
申请号：US551485
申请日：1990-07-12
Applicant: Kaoru Chujo , Mitsuo Kakuishi , Hirokazu Fukui
Inventor： Kaoru Chujo , Mitsuo Kakuishi , Hirokazu Fukui
IPC: H04B3/23
Abstract: An adaptive echo canceller for suppressing an echo in an input signal by a pseudo echo, includes a pseudo echo generation filter having a predicted impulse response sequence of an echo path as filter coefficients thereof for generating a pseudo echo, a coefficient renewal part for adaptively renewing the filter coefficients of the pseudo echo generation filter, and a part for suppressing an echo by the pseudo echo which is generated by the pseudo echo generation filter. The coefficient renewal part includes a part for dividing renewed filter coefficients into a plurality of groups each having a certain number of renewed filter coefficents, and a part for successively selecting one group with a predetermined period and carrying out a correction process with respect to the renewed filter coefficients within the selected group, where the correction process corrects an accumulation of errors of renewal processes.
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公开(公告)号：US4468749A
公开(公告)日：1984-08-28
申请号：US292275
申请日：1981-08-12
Applicant: Seiji Kato , Norio Ueno , Mitsuo Kakuishi
Inventor： Seiji Kato , Norio Ueno , Mitsuo Kakuishi
CPC classification number: H03H19/004
Abstract: An adjustable attenuator circuit in which sampled electric charges are partially transferred from a sampling capacitor to a charge dividing capacitor during a short time within each sampling period, and electric charges stored in the charge dividing capacitor are additively transferred to an integrating capacitor or are discharged to ground according to the content of a weighting coefficient which determines the attenuation factor of the adjustable attenuator circuit.
Abstract translation: 一种可调衰减器电路，其中在每个采样周期内短时间内采样电荷被部分地从采样电容器转移到充电分压电容器，并且存储在电荷分配电容器中的电荷被相加地传递到积分电容器或被放电到 根据确定可调衰减器电路的衰减系数的加权系数的内容来接地。
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5.发明授权Data receiving device for reproducing a received symbol from a received data signal 失效数据接收装置，用于从接收的数据信号再现接收的符号
公开(公告)号：US5638409A
公开(公告)日：1997-06-10
申请号：US342105
申请日：1994-11-18
Applicant: Yutaka Awata , Nobukazu Koizumi , Yasuo Ohtomo , Mitsuo Kakuishi
Inventor： Yutaka Awata , Nobukazu Koizumi , Yasuo Ohtomo , Mitsuo Kakuishi
IPC: H03M1/12 , H03H21/00 , H03L7/06 , H04B3/06 , H04J3/06 , H04L7/00 , H04L7/02 , H04L25/03 , H04L7/033
CPC classification number: H04L7/0062 , H04J3/0602 , H04L7/0083
Abstract: A data receiving device for reproducing a received symbol from a received data signal, includes a timing recovery circuit for controlling a phase of sampling the received data signal, by using pre-cursor information, the timing recovery circuit produces sampling phase control information by eliminating a high frequency component for the pre-cursor information, accumulating eliminated output, comparing accumulated output with a positive or a negative threshold value and subtracting the threshold value from compared output. The data receiving device further includes a masking circuit for masking the sampling phase control information when no-signal data or frame is detected in the received data signal.
Abstract translation: 一种用于从接收到的数据信号再现接收到的符号的数据接收装置包括：定时恢复电路，用于通过使用前置光标信息来控制对接收到的数据信号进行采样的相位，定时恢复电路通过消除 用于前置信息的高频分量，积累消除的输出，将累积输出与正阈值或负阈值进行比较，并从比较输出中减去阈值。 数据接收装置还包括掩蔽电路，用于在接收到的数据信号中检测无信号数据或帧时屏蔽采样相位控制信息。
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Patent Agency Ranking6.发明授权Signal processing system for use in a digital signal clock changing apparatus 失效用于数字信号时钟变换装置的信号处理系统
公开(公告)号：US5615235A
公开(公告)日：1997-03-25
申请号：US402205
申请日：1995-03-10
Applicant: Mitsuo Kakuishi , Tsuyoshi Ueshima
Inventor： Mitsuo Kakuishi , Tsuyoshi Ueshima
CPC classification number: H03M1/20 , H03M1/1235
Abstract: The present invention provides, a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP) in a small, inexpensive structure.
Abstract translation: 本发明提供了一种双系统A / D转换器，其提供比单系统A / D转换器实现的更高的转换精度的数字输出信号。 相反，通过使用具有较低转换精度的双系数D / A转换器，本发明提供了一种比由单系统D / A转换器实现的转换精度更高的模拟输出信号。 此外，数字信号时钟改变单元通过执行第一数字数据列的高采样产生数据，并且通过基于第一和第二时钟之间的定时差的内插处理将第二数字数据与第二时钟同步。 因此，通过使用两个脉冲编码调制编码器/解码器（PCM.CODEC）和一个数字信号处理器（DSP），以小而廉价的结构实现高精度A / D和D / A转换器装置。
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公开(公告)号：US5450452A
公开(公告)日：1995-09-12
申请号：US25555
申请日：1993-03-03
Applicant: Mitsuo Kakuishi , Yutaka Awata
Inventor： Mitsuo Kakuishi , Yutaka Awata
CPC classification number: H03L7/0992 , H03D3/241 , H03H21/0012 , H03L7/093 , H03B28/00
Abstract: A digital loop filter includes a first loop filter for generating first phase control information at variable time intervals on the basis of phase error information indicating a phase difference between a first signal and a second signal. A second loop filter detects a frequency deviation between the first and second signals from the phase error information and generates second phase control information with a period inversely proportional to the frequency deviation. An adder generates finalized phase control information obtained by adding the first phase control information and the second phase control information to each other.
Abstract translation: 数字环路滤波器包括第一环路滤波器，用于基于指示第一信号和第二信号之间的相位差的相位误差信息，以可变的时间间隔产生第一相位控制信息。 第二环路滤波器检测来自相位误差信息的第一和第二信号之间的频率偏差，并产生具有与频率偏差成反比的周期的第二相位控制信息。 加法器产生通过将第一相位控制信息和第二相位控制信息彼此相加而获得的最终相位控制信息。
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公开(公告)号：US5287406A
公开(公告)日：1994-02-15
申请号：US725838
申请日：1991-07-03
Applicant: Mitsuo Kakuishi
Inventor： Mitsuo Kakuishi
Abstract: A hybrid circuit includes a two-wire/four-wire conversion unit for forming an interface between a two-wire line and a four-wire line, and a digital balancing unit for canceling a return echo passing through an echo return route including the conversion unit. The digital balancing unit includes first through fourth parts. The first part determines values of elements of a ladder type circuit composed of resistors and capacitors. The ladder type circuit corresponds to an original equivalent circuit having an impedance obtained by viewing the two-wire line from the conversion unit. The second part generates an impedance function of the original equivalent circuit in the form of a z function in accordance with a bilinear transform using an over-sampling frequency. The third part generates filter coefficients of a digital filter by inserting the impedance function into a transfer function of the echo return route. The fourth part generates, from a signal transferred via the signal receiving terminal, an echo cancel signal by the digital filter having the filter coefficients generated by the third part and cancels the return echo by the echo cancel signal.
Abstract translation: 混合电路包括用于形成双线线路和四线制线路之间的接口的双线/四线转换单元，以及数字平衡单元，用于抵消通过包括转换的回波返回路线的返回回波 单元。 数字平衡单元包括第一至第四部分。 第一部分确定由电阻器和电容器组成的梯形电路元件的值。 梯形电路对应于具有通过从转换单元观看双线线路而获得的阻抗的原始等效电路。 第二部分根据使用过采样频率的双线性变换，以z函数的形式产生原始等效电路的阻抗函数。 第三部分通过将阻抗函数插入到回波返回路由的传递函数中来产生数字滤波器的滤波器系数。 第四部分从经由信号接收终端传送的信号产生具有由第三部分生成的滤波器系数的数字滤波器的回波消除信号，并通过回波消除信号来消除返回回波。
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9.发明授权Transforming adaptors for wave digital filter and balancing network using same 失效波形数字滤波器和平衡网络的转换适配器
公开(公告)号：US5249145A
公开(公告)日：1993-09-28
申请号：US679016
申请日：1991-04-30
Applicant: Mitsuo Kakuishi
Inventor： Mitsuo Kakuishi
IPC: H03H17/02
CPC classification number: H03H17/0201
Abstract: A balancing network of a wave digital type filter including 3-port pair transforming adaptors (21 to 26) connected in cascade each having a capacitor (C) and a resistor (R) as constituent elements and performing a filter operation function. There is no reflected wave from each port pair other than the two port pairs for the cascade connection of the transforming adaptors (22, 24, 26) each including resistor (R), that port pair is eliminated, and adjoining transforming adaptors (21, 23, 25) each including capacitor (C) are combined to form new 3-port pair combined transforming adaptors (41). Thus, it becomes possible to realize a filter operation by a lesser amount of operations than the sum of the amounts of operations by the 3-port pair transforming adaptors (21 to 26).
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公开(公告)号：US5781076A
公开(公告)日：1998-07-14
申请号：US764969
申请日：1996-12-13
Applicant: Takanori Iwamatsu , Mitsuo Kakuishi
Inventor： Takanori Iwamatsu , Mitsuo Kakuishi
CPC classification number: H04L27/38 , H04L27/362
Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator includes first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also includes a parallel-to-serial converter to successively select the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.
Abstract translation: 具有正交幅度调制（QAM）方案的数字调制器和数字解调器，被设计为调制或解调RZ编码的基带信号。 数字调制器包括第一至第四滚降滤波器以及连接到第二和第四滚降滤波器的第一和第二反相器。 还包括并行转换器，用于连续选择第一滚降滤波器，第三滚降滤波器，第一反相器和第二反相器的输出。 D / A转换器将所选择的数字信号流转换成模拟信号。 滚降滤波器和反相器以预定的时钟频率工作，而并行到串行转换器和D / A转换器以预定时钟频率的四倍的频率工作。 数字解调器反转上述调制过程以再现基带信号。
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