公开(公告)号：US5615235A

公开(公告)日：1997-03-25

申请号：US402205

申请日：1995-03-10

Applicant: Mitsuo Kakuishi ,  Tsuyoshi Ueshima

Inventor： Mitsuo Kakuishi ,  Tsuyoshi Ueshima

IPC: H03M1/12 ,  H03M1/20 ,  H04L7/00

CPC classification number: H03M1/20 ,  H03M1/1235

Abstract: The present invention provides, a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP) in a small, inexpensive structure.

Abstract translation: 本发明提供了一种双系统A / D转换器，其提供比单系统A / D转换器实现的更高的转换精度的数字输出信号。 相反，通过使用具有较低转换精度的双系数D / A转换器，本发明提供了一种比由单系统D / A转换器实现的转换精度更高的模拟输出信号。 此外，数字信号时钟改变单元通过执行第一数字数据列的高采样产生数据，并且通过基于第一和第二时钟之间的定时差的内插处理将第二数字数据与第二时钟同步。 因此，通过使用两个脉冲编码调制编码器/解码器（PCM.CODEC）和一个数字信号处理器（DSP），以小而廉价的结构实现高精度A / D和D / A转换器装置。

公开(公告)号：US5610943A

公开(公告)日：1997-03-11

申请号：US436928

申请日：1995-05-08

Applicant: Mitsuo Kakuishi ,  Tsuyoshi Ueshima

Inventor： Mitsuo Kakuishi ,  Tsuyoshi Ueshima

IPC: H03M1/12 ,  H03M1/20 ,  H04B14/02 ,  H03H17/02

CPC classification number: H03M1/20 ,  H03M1/1235

Abstract: The present invention provides a two-system A/D converter, which provides a digital output signal with a higher conversion precision than is achieved by a single-system A/D converter. Conversely, by using a two-system D/A converter with a lower conversion precision, the present invention provides an analog output signal with a higher conversion precision than is achieved by a single-system D/A converter. Further, a digital signal clock changing unit produces data by performing high sampling of the first digital data trains, and the second digital data is synchronized with a second clock through an interpolation processing based on the timing difference between the first and second clocks. A high-precision A/D and D/A converter apparatus is thus realized by using two pulse code modulation coder/decoders (PCM.CODECs) and one digital signal processor (DSP).

Abstract translation: 本发明提供了一种双系统A / D转换器，其提供比由单系统A / D转换器实现的更高的转换精度的数字输出信号。 相反，通过使用具有较低转换精度的双系数D / A转换器，本发明提供了一种比由单系统D / A转换器实现的转换精度更高的模拟输出信号。 此外，数字信号时钟改变单元通过执行第一数字数据列的高采样产生数据，并且通过基于第一和第二时钟之间的定时差的内插处理将第二数字数据与第二时钟同步。 因此，通过使用两个脉冲编码调制编码器/解码器（PCM.CODEC）和一个数字信号处理器（DSP）来实现高精度A / D和D / A转换器装置。

公开(公告)号：US5659609A

公开(公告)日：1997-08-19

申请号：US503620

申请日：1995-07-18

Applicant: Nobukazu Koizumi ,  Mitsuo Kakuishi ,  Yutaka Awata

Inventor： Nobukazu Koizumi ,  Mitsuo Kakuishi ,  Yutaka Awata

IPC: H04B3/06 ,  H04B1/10 ,  H04B3/23 ,  H04B3/26

CPC classification number: H04B3/23

Abstract: An echo canceller is disclosed which generates an echo replica based on a transmit signal to cancel an echo. The echo canceller includes a linear echo canceller circuit for generating an echo replica of the transmit signal in the absence of distortion. The echo canceller further includes a waveform-distortion compensation circuit, coupled with the linear echo canceller circuit, for generating an echo replica for compensating waveform distortion occurred in an echo response when the transmit signal is distorted. In the echo canceller, the echo is canceled by use of the echo replica generated in the linear echo canceller circuit in the absence of distortion in the transmit signal, and is canceled by use of the echo replica generated in the waveform-distortion compensation circuit when the transmit signal is distorted.

Abstract translation: 公开了一种回波消除器，其基于发送信号产生回波复制以消除回波。 回波消除器包括用于在不存在失真的情况下产生发射信号的回波复制品的线性回波消除器电路。 回波消除器还包括与线性回波消除器电路耦合的波形失真补偿电路，用于产生用于在发送信号失真时在回波响应中发生的波形失真的回波复制品。 在回波消除器中，通过在发送信号中没有失真的情况下，通过使用在线性回波消除器电路中生成的回波副本来消除回波，并且通过使用在波形失真补偿电路中产生的回波复制来解除回波 发送信号失真。

公开(公告)号：US5471507A

公开(公告)日：1995-11-28

申请号：US122500

申请日：1993-09-28

Applicant: Yutaka Awata ,  Mitsuo Kakuishi

Inventor： Yutaka Awata ,  Mitsuo Kakuishi

IPC: G06F1/32 ,  H04L7/04 ,  H04Q1/30 ,  H04Q1/50 ,  H04L27/06

CPC classification number: H04Q1/50 ,  G06F1/32 ,  H04Q1/30 ,  H04L2007/047

Abstract: An input analog signal having a periodicity is converted into one-bit digital signals by an A/D converter (42), and the one-bit digital signals are converted into parallel signals by a serial-to-parallel converter (43). A correlation between the parallel signals and a reference signal string is detected by a correlation device (45). When the correlation is detected, a hold circuit (48) holds detection of the correlation and hence outputs a tone signal detection result. With the above simple, low power consumption circuit structure, the tone signal can be detected.

Abstract translation: PCT No.PCT / JP93 / 00100 Sec。 371日期：1993年9月28日 102（e）日期1993年9月28日PCT 1993年1月28日PCT公布。 公开号WO93 / 15580 日期：1993年5月8日。具有周期性的输入模拟信号由A / D转换器（42）转换成1位数字信号，一位数字信号通过串行到并行转换成并行信号 转换器（43）。 相关装置（45）检测并行信号和参考信号串之间的相关性。 当检测到相关时，保持电路（48）保持相关的检测，从而输出音调信号检测结果。 利用上述简单的低功耗电路结构，可以检测音调信号。

公开(公告)号：US5151937A

公开(公告)日：1992-09-29

申请号：US551485

申请日：1990-07-12

Applicant: Kaoru Chujo ,  Mitsuo Kakuishi ,  Hirokazu Fukui

Inventor： Kaoru Chujo ,  Mitsuo Kakuishi ,  Hirokazu Fukui

IPC: H04B3/23

CPC classification number: H04B3/231 ,  H04B3/234 ,  H04B3/238

Abstract: An adaptive echo canceller for suppressing an echo in an input signal by a pseudo echo, includes a pseudo echo generation filter having a predicted impulse response sequence of an echo path as filter coefficients thereof for generating a pseudo echo, a coefficient renewal part for adaptively renewing the filter coefficients of the pseudo echo generation filter, and a part for suppressing an echo by the pseudo echo which is generated by the pseudo echo generation filter. The coefficient renewal part includes a part for dividing renewed filter coefficients into a plurality of groups each having a certain number of renewed filter coefficents, and a part for successively selecting one group with a predetermined period and carrying out a correction process with respect to the renewed filter coefficients within the selected group, where the correction process corrects an accumulation of errors of renewal processes.

公开(公告)号：US4468749A

公开(公告)日：1984-08-28

申请号：US292275

申请日：1981-08-12

Applicant: Seiji Kato ,  Norio Ueno ,  Mitsuo Kakuishi

Inventor： Seiji Kato ,  Norio Ueno ,  Mitsuo Kakuishi

IPC: H03H19/00 ,  H03G3/00

CPC classification number: H03H19/004

Abstract: An adjustable attenuator circuit in which sampled electric charges are partially transferred from a sampling capacitor to a charge dividing capacitor during a short time within each sampling period, and electric charges stored in the charge dividing capacitor are additively transferred to an integrating capacitor or are discharged to ground according to the content of a weighting coefficient which determines the attenuation factor of the adjustable attenuator circuit.

Abstract translation: 一种可调衰减器电路，其中在每个采样周期内短时间内采样电荷被部分地从采样电容器转移到充电分压电容器，并且存储在电荷分配电容器中的电荷被相加地传递到积分电容器或被放电到 根据确定可调衰减器电路的衰减系数的加权系数的内容来接地。

公开(公告)号：US5781076A

公开(公告)日：1998-07-14

申请号：US764969

申请日：1996-12-13

Applicant: Takanori Iwamatsu ,  Mitsuo Kakuishi

Inventor： Takanori Iwamatsu ,  Mitsuo Kakuishi

IPC: H04L27/36 ,  H04L27/38

CPC classification number: H04L27/38 ,  H04L27/362

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator includes first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also includes a parallel-to-serial converter to successively select the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract translation: 具有正交幅度调制（QAM）方案的数字调制器和数字解调器，被设计为调制或解调RZ编码的基带信号。 数字调制器包括第一至第四滚降滤波器以及连接到第二和第四滚降滤波器的第一和第二反相器。 还包括并行转换器，用于连续选择第一滚降滤波器，第三滚降滤波器，第一反相器和第二反相器的输出。 D / A转换器将所选择的数字信号流转换成模拟信号。 滚降滤波器和反相器以预定的时钟频率工作，而并行到串行转换器和D / A转换器以预定时钟频率的四倍的频率工作。 数字解调器反转上述调制过程以再现基带信号。

公开(公告)号：US5481564A

公开(公告)日：1996-01-02

申请号：US733983

申请日：1991-07-22

Applicant: Mitsuo Kakuishi ,  Yutaka Awata ,  Norio Ueno ,  Seiji Miyoshi ,  Norio Murakami ,  Atsushi Manabe

Inventor： Mitsuo Kakuishi ,  Yutaka Awata ,  Norio Ueno ,  Seiji Miyoshi ,  Norio Murakami ,  Atsushi Manabe

IPC: H04L25/03 ,  H03H7/30

CPC classification number: H04L25/03885 ,  H04L25/03057

Abstract: A digital adaptive equalizer equalizes received signals through digital filtering operations by changing filtering coefficients. It comprises a coefficient calculating unit for calculating the filtering coefficients by using one kind of parameters, such as distance, as an input to a function corresponding to the filtering coefficients and a filtering operation executing unit for executing digital filtering operations based on the filtering coefficients. A variable lag filter for adjusting the phase delay of received received signals is provided. A coefficient converting unit calculates a part or all of tap coefficients of the filter using at least one piece of timing control information.

Abstract translation: 数字自适应均衡器通过改变滤波系数通过数字滤波操作来均衡接收信号。 它包括：系数计算单元，用于通过使用诸如距离的一种参数来计算滤波系数，作为与滤波系数相对应的函数的输入;以及滤波操作执行单元，用于基于滤波系数执行数字滤波操作。 提供了用于调整接收到的接收信号的相位延迟的可变滞后滤波器。 系数转换单元使用至少一条定时控制信息来计算滤波器的抽头系数的一部分或全部。

公开(公告)号：US5399985A

公开(公告)日：1995-03-21

申请号：US33001

申请日：1993-03-18

Applicant: Yutaka Awata ,  Nobukazu Koizumi ,  Yasuo Ohtomo ,  Mitsuo Kakuishi

Inventor： Yutaka Awata ,  Nobukazu Koizumi ,  Yasuo Ohtomo ,  Mitsuo Kakuishi

IPC: G11B20/14 ,  H03L7/06 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H04L7/033 ,  H03K5/13 ,  H03L7/087 ,  H03L7/089 ,  H03L7/18

CPC classification number: H03L7/0992 ,  H03L7/107

Abstract: The invention provides a digital PLL circuit wherein the integration time constant of a random walk filter can be varied adaptively in response to a frequency error. A master clock signal having a frequency equal to N (integral number) times that of an input clock signal is normally divided by N by a divider, and the division output of the divider and the input clock signal are compared in phase with each other by a phase comparator. The dividing ratio of the divider is temporarily varied in accordance with a result of the comparison so as to make the phases of the division output and the input clock signal coincide with each other to establish synchronism between them. A variable step number random walk filter is interposed between the phase comparator and the divider and has a selectively settable integration time constant, and an integration time constant setting circuit varies the step number of the random walk filter in accordance with information of a last phase controlling direction or directions and information of a phase controlling direction at present to vary the integration time constant of the random walk filter.

Abstract translation: 本发明提供一种数字PLL电路，其中随机游走滤波器的积分时间常数可以响应于频率误差而自适应变化。 具有等于​​输入时钟信号的N（整数）倍的频率的主时钟信号通常被除法器除以N，并且除法器和输入时钟信号的除法输出被相位相互比较， 相位比较器。 根据比较结果，分频器的分频比暂时变化，从而使分频输出和输入时钟信号的相位相互一致，从而建立它们之间的同步。 可变步数随机游走滤波器插入在相位比较器和分频器之间，并且具有可选择的可设定积分时间常数，并且积分时间常数设定电路根据最后相位控制的信息改变随机游走滤波器的步数 目前的相位控制方向的方向或方向和信息，以改变随机游走滤波器的积分时间常数。

公开(公告)号：US5638409A

公开(公告)日：1997-06-10

申请号：US342105

申请日：1994-11-18

Applicant: Yutaka Awata ,  Nobukazu Koizumi ,  Yasuo Ohtomo ,  Mitsuo Kakuishi

Inventor： Yutaka Awata ,  Nobukazu Koizumi ,  Yasuo Ohtomo ,  Mitsuo Kakuishi

IPC: H03M1/12 ,  H03H21/00 ,  H03L7/06 ,  H04B3/06 ,  H04J3/06 ,  H04L7/00 ,  H04L7/02 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L7/0062 ,  H04J3/0602 ,  H04L7/0083

Abstract: A data receiving device for reproducing a received symbol from a received data signal, includes a timing recovery circuit for controlling a phase of sampling the received data signal, by using pre-cursor information, the timing recovery circuit produces sampling phase control information by eliminating a high frequency component for the pre-cursor information, accumulating eliminated output, comparing accumulated output with a positive or a negative threshold value and subtracting the threshold value from compared output. The data receiving device further includes a masking circuit for masking the sampling phase control information when no-signal data or frame is detected in the received data signal.

Abstract translation: 一种用于从接收到的数据信号再现接收到的符号的数据接收装置包括：定时恢复电路，用于通过使用前置光标信息来控制对接收到的数据信号进行采样的相位，定时恢复电路通过消除 用于前置信息的高频分量，积累消除的输出，将累积输出与正阈值或负阈值进行比较，并从比较输出中减去阈值。 数据接收装置还包括掩蔽电路，用于在接收到的数据信号中检测无信号数据或帧时屏蔽采样相位控制信息。