公开(公告)号：US09262099B2

公开(公告)日：2016-02-16

申请号：US14009213

申请日：2012-03-22

申请人： Myoung Kyu Seo ,  Yong Soo Kim

发明人： Myoung Kyu Seo ,  Yong Soo Kim

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0629 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

摘要： Provided are a non-volatile memory device, an electronic control system, and a method of operating the non-volatile memory device. A non-volatile memory device according to an embodiment of the present invention includes a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages. A plurality of X-decoders are at least one-to-one connected to the first and second NAND cell arrays. A control logic controls the plurality of X-decoders to simultaneously sense data of a first page corresponding to a start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages.

摘要翻译： 提供了非易失性存储器件，电子控制系统和操作非易失性存储器件的方法。 根据本发明的实施例的非易失性存储器件包括包括第一组页面的第一NAND单元阵列和包括第二组页面的第二NAND单元阵列。 多个X解码器至少一对一连接到第一和第二NAND单元阵列。 控制逻辑控制多个X解码器，以从第一组页面中同时感测来自第一组页面的对应于起始地址的第一页面的数据，以及第二页面之后的第一页面之后的第二页面的数据。

公开(公告)号：US20140040538A1

公开(公告)日：2014-02-06

申请号：US14009221

申请日：2012-03-22

申请人： Myoung Kyu Seo ,  Tae Sun Hwang

发明人： Myoung Kyu Seo ,  Tae Sun Hwang

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/105 ,  G11C16/24

摘要： A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory.

摘要翻译： 公开了一种在包括NAND单元阵列的存储器中写入数据的方法，其中数据输出装置仅通过将数据和用于写入数据的起始地址发送到存储器来完成写入处理。

公开(公告)号：US07345925B2

公开(公告)日：2008-03-18

申请号：US11426387

申请日：2006-06-26

申请人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

发明人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/14

摘要： Erasure methods for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied to the source region starting at a first time. While continuing to apply the first nonzero voltage to the source region, a second voltage having an opposite polarity to the first voltage is applied to the gate electrode starting at a second time later than the first time. The second voltage may increase in magnitude, e.g., stepwise, linearly and/or along a curve, after the second time.

摘要翻译： 一种非易失性存储单元的擦除方法，包括基板上的栅极电极，栅电极各侧的基板中的源极和漏极区域以及介于栅电极和基板之间的电荷存储层。 从第一次开始，向源区域施加非零的第一电压。 在继续向源极区域施加第一非零电压的同时，比第一时间晚的第二时间将栅极电极施加具有与第一电压相反的极性的第二电压。 在第二次之后，第二电压的幅度可以例如逐步地，线性地和/或沿曲线增加。

公开(公告)号：US20070036003A1

公开(公告)日：2007-02-15

申请号：US11426387

申请日：2006-06-26

申请人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

发明人： Geum-Jong Bae ,  Myoung-Kyu Seo ,  In-Wook Cho ,  Byoung-Jin Lee ,  Jin-Hee Kim ,  Myung-Yoon Um ,  Geon-Woo Park ,  Sang-Won Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/14

摘要： Erasure methods are provided for a nonvolatile memory cell that includes a gate electrode on a substrate, source and drain regions in the substrate at respective sides of the gate electrode, and a charge storage layer interposed between the gate electrode and the substrate. A nonzero first voltage is applied to the source region starting at a first time. While continuing to apply the first nonzero voltage to the source region, a second voltage having an opposite polarity to the first voltage is applied to the gate electrode starting at a second time later than the first time. The second voltage may increase in magnitude, e.g., stepwise, linearly and/or along a curve, after the second time.

摘要翻译： 提供了一种非易失性存储单元的擦除方法，该非易失性存储单元包括衬底上的栅电极，栅电极各侧的衬底中的源区和漏区以及置于栅电极和衬底之间的电荷存储层。 从第一次开始，向源区域施加非零的第一电压。 在继续向源极区域施加第一非零电压的同时，比第一时间晚的第二时间将栅极电极施加具有与第一电压相反的极性的第二电压。 在第二次之后，第二电压的幅度可以例如逐步地，线性地和/或沿曲线增加。

公开(公告)号：US20140223080A1

公开(公告)日：2014-08-07

申请号：US14009213

申请日：2012-03-22

申请人： Myoung Kyu Seo ,  Yong Soo Kim

发明人： Myoung Kyu Seo ,  Yong Soo Kim

IPC分类号： G06F3/06

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/0629 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

摘要： Provided are a non-volatile memory device, an electronic control system, and a method of operating the non-volatile memory device. A non-volatile memory device according to an embodiment of the present invention includes a first NAND cell array including a first group of pages, and a second NAND cell array including a second group of pages. A plurality of X-decoders are at least one-to-one connected to the first and second NAND cell arrays. A control logic controls the plurality of X-decoders to simultaneously sense data of a first page corresponding to a start address from among the first group of pages, and data of a second page subsequent to the first page from among the second group of pages.

摘要翻译： 提供了非易失性存储器件，电子控制系统和操作非易失性存储器件的方法。 根据本发明的实施例的非易失性存储器件包括包括第一组页面的第一NAND单元阵列和包括第二组页面的第二NAND单元阵列。 多个X解码器至少一对一连接到第一和第二NAND单元阵列。 控制逻辑控制多个X解码器，以从第一组页面中同时感测来自第一组页面的对应于起始地址的第一页面的数据，以及第二页面之后的第一页面之后的第二页面的数据。

公开(公告)号：US20070008780A1

公开(公告)日：2007-01-11

申请号：US11452899

申请日：2006-06-15

申请人： Jong-Hoon Jung ,  Myoung-Kyu Seo ,  Hyo-Sang Lee ,  Hoon-Jin Bang

发明人： Jong-Hoon Jung ,  Myoung-Kyu Seo ,  Hyo-Sang Lee ,  Hoon-Jin Bang

IPC分类号： G11C11/34 ,  G11C16/06 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C5/143

摘要： A word line driving circuit, which may include a read voltage generator and a word line driver. The read voltage generator may precharge a clamp capacitor with a power supply voltage to stably generate a read voltage in response to a read command. A capacitance of the clamp capacitor may be varied to compensate for a fluctuation of a power supply voltage level. The word line driver may distribute electric charges precharged in the clamp capacitor to a word line in response to a word line selecting signal. Therefore, the word line driving circuit may reduce unnecessary power consumption in a standby mode by operating the word line rapidly with charge sharing in a read mode.

摘要翻译： 字线驱动电路，其可以包括读取电压发生器和字线驱动器。 读取电压发生器可以用电源电压对钳位电容器进行预充电，以响应于读取命令稳定地产生读取电压。 可以改变钳位电容器的电容以补偿电源电压电平的波动。 字线驱动器可以响应于字线选择信号将预充电在钳位电容器中的电荷分配到字线。 因此，字线驱动电路可以通过在读取模式下通过电荷共享快速操作字线来减少待机模式下的不必要的功耗。

公开(公告)号：US07050334B2

公开(公告)日：2006-05-23

申请号：US10921798

申请日：2004-08-20

申请人： Tae-Seong Kim ,  Myoung-Kyu Seo

发明人： Tae-Seong Kim ,  Myoung-Kyu Seo

IPC分类号： G11C16/00

CPC分类号： G11C16/12 ,  G11C16/24

摘要： Provided are a program control circuit for flash memory devices and a control method utilizing such a circuit for controlling the bit line voltage level during programming operations for flash memory devices that include memory cells arranged in the form of a matrix, in which each of the memory cells is connected to a word line, a bit line, and a source line and which provides a program current to the bit line. The program control circuit includes a voltage level sensing control portion, a switching control portion, a current sink and a switching circuit. The voltage level sensing control portion is enabled or disabled in response to a first program control signal and compares the voltage of a bit line connected to a memory cell being programmed with a reference voltage and outputs a voltage control signal corresponding to the result of the comparison. The switching control portion outputs a switching bias signal in response to the voltage control signal and a second program control signal. The current sink provides a predetermined current to a ground voltage in response to a reference bias signal. The switching circuit, which is connected between the bit line and the current sink, is turned on or off in response to the switching bias signal.

摘要翻译： 提供了一种用于闪速存储器件的程序控制电路和利用这种电路控制方法的控制方法，该电路用于在包括以矩阵形式布置的存储器单元的闪速存储器件的编程操作期间控制位线电压电平，其中存储器 单元连接到字线，位线和源极线，并且向位线提供程序电流。 程序控制电路包括电压电平检测控制部分，开关控制部分，电流吸收器和开关电路。 电压电平检测控制部分响应于第一程序控制信号被使能或禁止，并且将连接到正被编程的存储器单元的位线的电压与参考电压进行比较并输出与比较结果相对应的电压控制信号 。 切换控制部分响应于电压控制信号和第二程序控制信号输出切换偏置信号。 电流吸收器响应于参考偏置信号而向接地电压提供预定电流。 连接在位线和电流吸收器之间的开关电路响应于开关偏置信号而导通或截止。

公开(公告)号：US09292430B2

公开(公告)日：2016-03-22

申请号：US14009221

申请日：2012-03-22

申请人： Myoung Kyu Seo ,  Tae Sun Hwang

发明人： Myoung Kyu Seo ,  Tae Sun Hwang

IPC分类号： G06F12/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/06 ,  G11C16/24

CPC分类号： G06F12/0246 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C16/105 ,  G11C16/24

摘要： A method of writing data in a memory comprising a NAND cell array is disclosed, wherein a data output device completes the writing process only by transmitting the data and a start address for writing the data to the memory.

摘要翻译： 公开了一种在包括NAND单元阵列的存储器中写入数据的方法，其中数据输出装置仅通过将数据和用于写入数据的起始地址发送到存储器来完成写入处理。

公开(公告)号：US07394701B2

公开(公告)日：2008-07-01

申请号：US11452899

申请日：2006-06-15

申请人： Jong-Hoon Jung ,  Myoung-Kyu Seo ,  Hyo-Sang Lee ,  Hoon-Jin Bang

发明人： Jong-Hoon Jung ,  Myoung-Kyu Seo ,  Hyo-Sang Lee ,  Hoon-Jin Bang

IPC分类号： G11C16/08 ,  G11C16/30 ,  G11C16/26

CPC分类号： G11C8/08 ,  G11C5/143

摘要： A word line driving circuit includes a read voltage generator and a word line driver. The read voltage generator precharges a clamp capacitor with a power supply voltage to stably generate a read voltage in response to a read command. A capacitance of the clamp capacitor is varied to compensate for a fluctuation of a power supply voltage level. The word line driver distributes electric charges precharged in the clamp capacitor to a word line in response to a word line selecting signal. Therefore, the word line driving circuit reduces unnecessary power consumption in a standby mode by operating the word line rapidly with charge sharing in a read mode.

摘要翻译： 字线驱动电路包括读电压发生器和字线驱动器。 读取电压发生器对具有电源电压的钳位电容器进行预充电，以响应于读取命令稳定地产生读取电压。 改变钳位电容器的电容以补偿电源电压电平的波动。 字线驱动器响应于字线选择信号将预充电在钳位电容器中的电荷分配到字线。 因此，字线驱动电路通过在读取模式下通过电荷共享快速地操作字线来减少待机模式下的不必要的功耗。

公开(公告)号：US20050047214A1

公开(公告)日：2005-03-03

申请号：US10921798

申请日：2004-08-20

申请人： Tae-Seong Kim ,  Myoung-Kyu Seo

发明人： Tae-Seong Kim ,  Myoung-Kyu Seo

IPC分类号： G11C16/12 ,  G11C16/24 ,  G11C11/34

CPC分类号： G11C16/12 ,  G11C16/24

摘要： Provided are a program control circuit for flash memory devices and a control method utilizing such a circuit for controlling the bit line voltage level during programming operations for flash memory devices that include memory cells arranged in the form of a matrix, in which each of the memory cells is connected to a word line, a bit line, and a source line and which provides a program current to the bit line. The program control circuit includes a voltage level sensing control portion, a switching control portion, a current sink and a switching circuit. The voltage level sensing control portion is enabled or disabled in response to a first program control signal and compares the voltage of a bit line connected to a memory cell being programmed with a reference voltage and outputs a voltage control signal corresponding to the result of the comparison. The switching control portion outputs a switching bias signal in response to the voltage control signal and a second program control signal. The current sink provides a predetermined current to a ground voltage in response to a reference bias signal. The switching circuit, which is connected between the bit line and the current sink, is turned on or off in response to the switching bias signal.

摘要翻译： 提供了一种用于闪速存储器件的程序控制电路和利用这种电路控制方法的控制方法，该电路用于在包括以矩阵形式布置的存储器单元的闪速存储器件的编程操作期间控制位线电压电平，其中存储器 单元连接到字线，位线和源极线，并且向位线提供程序电流。 程序控制电路包括电压电平检测控制部分，开关控制部分，电流吸收器和开关电路。 电压电平检测控制部分响应于第一程序控制信号被使能或禁止，并且将连接到正被编程的存储器单元的位线的电压与参考电压进行比较并输出与比较结果相对应的电压控制信号 。 切换控制部分响应于电压控制信号和第二程序控制信号输出切换偏置信号。 电流吸收器响应于参考偏置信号而向接地电压提供预定电流。 连接在位线和电流吸收器之间的开关电路响应于开关偏置信号而导通或截止。