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    Dynamic scaling of graphics processor execution resources
    1.
    发明授权
    Dynamic scaling of graphics processor execution resources 有权

    公开(公告)号：US10025367B2

    公开(公告)日：2018-07-17

    申请号：US14463573

    申请日：2014-08-19

    Applicant: Nikos Kaburlasos ,  Eric Samson

    Inventor： Nikos Kaburlasos ,  Eric Samson

    IPC: G06F1/32

    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

    DRAM selective self refresh
    2.
    发明授权
    DRAM selective self refresh 有权
    DRAM选择性自刷新

    公开(公告)号：US08209480B2

    公开(公告)日：2012-06-26

    申请号：US12835525

    申请日：2010-07-13

    Applicant: Nikos Kaburlasos ,  Jim Kardaeh

    Inventor： Nikos Kaburlasos ,  Jim Kardaeh

    IPC: G06F12/02

    CPC classification number: G06F12/0292 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067 ,  Y02D10/13

    Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

    Abstract translation: 在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑， 在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。 可以描述其他实施例。

    Device, system, and method of memory allocation
    3.
    发明授权
    Device, system, and method of memory allocation 有权
    设备，系统和内存分配方法

    公开(公告)号：US08095725B2

    公开(公告)日：2012-01-10

    申请号：US11967296

    申请日：2007-12-31

    Applicant: Jim Kardach ,  Nikos Kaburlasos

    Inventor： Jim Kardach ,  Nikos Kaburlasos

    IPC: G06F12/02

    CPC classification number: G11C11/40618 ,  G06F12/0223 ,  G06F12/06 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40622 ,  Y02D10/13

    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

    Abstract translation: 设备，系统和内存分配方法。 例如，一种装置包括：包括存储数据的多个动态随机存取存储器（DRAM）单元的双列直插存储器模块（DIMM），其中每个DRAM单元包括多个存储体，并且每个存储体被分成多个 的子银行; 以及存储器管理单元，用于将所述DIMM的交织子组的一组分配给操作系统的存储器页，其中所述交织子组的组合存储器大小等于所述存储器页的大小 操作系统。

    DRAM selective self refresh
    4.
    发明授权
    DRAM selective self refresh 有权
    DRAM选择性自刷新

    公开(公告)号：US07757039B2

    公开(公告)日：2010-07-13

    申请号：US11901502

    申请日：2007-09-18

    Applicant: Nikos Kaburlasos ,  Jim Kardach

    Inventor： Nikos Kaburlasos ,  Jim Kardach

    IPC: G06F12/02 ,  G06F1/32

    CPC classification number: G06F12/0292 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067 ,  Y02D10/13

    Abstract: In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described.

    Abstract translation: 在一些实施例中，电子设备包括通信接口，输入/输出接口，处理器和在电子设备中收集与第一通信设备相关联的第一标识符和与第二通信设备相关联的第二标识符的逻辑， 在电子设备和第一通信设备之间建立通信连接的逻辑，以及在电子设备中启动第一通信设备和第二通信设备之间的通信连接的连接请求的逻辑。 可以描述其他实施例。

    Clock-gated random access memory
    5.
    发明授权
    Clock-gated random access memory 有权
    时钟门控随机存取存储器

    公开(公告)号：US07478214B2

    公开(公告)日：2009-01-13

    申请号：US11325887

    申请日：2006-01-04

    Applicant: Nikos Kaburlasos

    Inventor： Nikos Kaburlasos

    IPC: G06F13/00 ,  G06F12/00

    CPC classification number: G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method and apparatus for gating a clock signal to one or more embedded blocks of a random access memory (RAM), is described. In one embodiment, a clock gating block is coupled to a RAM EBB, the clock-gating block to provide a RAM clock when receiving read and write enable signals and to provide a gated clock signal when the RAM EBB is idle. In another embodiment, a clock gating block is coupled to a RAM bank, having a plurality of RAM EBBs, the clock-gating block to provide a RAM clock to the RAM bank when receiving read and write enable signals and to provide a gated clock signal to the RAM bank when the RAM bank is idle.

    Abstract translation: 描述了用于将时钟信号选通到随机存取存储器（RAM）的一个或多个嵌入块的方法和装置。 在一个实施例中，时钟门控模块耦合到RAM EBB，时钟门控模块，当接收到读和写使能信号时提供RAM时钟，并在RAM EBB空闲时提供选通时钟信号。 在另一个实施例中，时钟门控模块耦合到具有多个RAM EBB的RAM存储体，时钟门控模块在接收到读和写使能信号时向RAM存储体提供RAM时钟，并提供门控时钟信号 到RAM存储区时，RAM存储空闲。

    DYNAMIC SCALING OF GRAPHICS PROCESSOR EXECUTION RESOURCES
    8.
    发明申请
    DYNAMIC SCALING OF GRAPHICS PROCESSOR EXECUTION RESOURCES 有权
    图形处理器执行资源的动态缩放

    公开(公告)号：US20160054782A1

    公开(公告)日：2016-02-25

    申请号：US14463573

    申请日：2014-08-19

    Applicant: NIKOS KABURLASOS ,  Eric Samson

    Inventor： NIKOS KABURLASOS ,  Eric Samson

    IPC: G06F1/32

    CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3265 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/153 ,  Y02D10/171 ,  Y02D10/172

    Abstract: In one embodiment execution units, graphics cores, or graphics sub-cores can be dynamically scaled across a frame of graphics operations. Available execution units within each graphics core may be scaled using utilization metrics such as the current utilization rate of the execution units and the submission of new draw calls. In one embodiment, one of more of the sub-cores within each graphics core may be enable or disabled based on current or past utilization of the sub-cores based on a set of current graphics operations.

    Abstract translation: 在一个实施例中，执行单元，图形核心或图形子核心可以在图形操作的框架上动态缩放。 每个图形核心中的可用执行单元可以使用诸如执行单元的当前使用率和提交新的绘图调用之类的利用度量来缩放。 在一个实施例中，基于当前图形操作的集合，可以基于子核的当前或过去利用来启用或禁用每个图形核心内的多个子核中的一个。

    Device, system, and method of memory allocation
    10.
    发明授权
    Device, system, and method of memory allocation 有权
    设备，系统和内存分配方法

    公开(公告)号：US08843702B2

    公开(公告)日：2014-09-23

    申请号：US13332526

    申请日：2011-12-21

    Applicant: Jlm Kardach ,  Nikos Kaburlasos

    Inventor： Jlm Kardach ,  Nikos Kaburlasos

    IPC: G06F12/06 ,  G11C11/406

    CPC classification number: G11C11/40618 ,  G06F12/0223 ,  G06F12/06 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C7/1072 ,  G11C11/406 ,  G11C11/40622 ,  Y02D10/13

    Abstract: Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System.

    Abstract translation: 设备，系统和内存分配方法。 例如，一种装置包括：包括存储数据的多个动态随机存取存储器（DRAM）单元的双列直插存储器模块（DIMM），其中每个DRAM单元包括多个存储体，并且每个存储体被分成多个 的子银行; 以及存储器管理单元，用于将所述DIMM的交织子组的一组分配给操作系统的存储器页，其中所述交织子组的组合存储器大小等于所述存储器页的大小 操作系统。

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