公开(公告)号：US09312385B2

公开(公告)日：2016-04-12

申请号：US14239249

申请日：2012-06-07

申请人： Daisuke Matsumoto ,  Naoki Tega ,  Yasuhiro Shimamoto

发明人： Daisuke Matsumoto ,  Naoki Tega ,  Yasuhiro Shimamoto

IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/16

CPC分类号： H01L29/7838 ,  H01L27/0883 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66674 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802

摘要： A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n−-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.

摘要翻译： 提供了一种用于改善半导体器件（DMOSFET）的特性的技术。 半导体器件被配置为包括：设置在SiC衬底（106）的第一表面侧的上部的n型源极层（102）; 围绕源层并具有沟道区的p体层（103）; 与p体层（103）接触的n型漂移层（107）; 栅极电极，其经由栅极绝缘膜设置在所述沟道区域的上部; 并且设置在p体层（103）中的第一p +层（109）延伸到n +源极层（102）下方的部分，并且用作具有高于p的杂质浓度的掩埋半导体区域 身体层（103）。 以这种方式，由于第一p +层（109）形成在p体层（103）的中间，所以可以降低p体层（103）的扩散阻力。 因此，可以使寄生双极晶体管更难以导通。

公开(公告)号：US20080048249A1

公开(公告)日：2008-02-28

申请号：US11773842

申请日：2007-07-05

申请人： NAOKI TEGA ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

发明人： NAOKI TEGA ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

摘要翻译： 在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置 栅极绝缘膜（d> = 0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近连续平滑地接合。 通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。 因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

公开(公告)号：US07709315B2

公开(公告)日：2010-05-04

申请号：US11773842

申请日：2007-07-05

申请人： Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

发明人： Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

IPC分类号： H01L21/8238

CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

摘要翻译： 在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置 栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。 通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。 因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

公开(公告)号：US09117836B2

公开(公告)日：2015-08-25

申请号：US13349430

申请日：2012-01-12

申请人： Naoki Tega ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

发明人： Naoki Tega ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

IPC分类号： H01L21/28 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L29/7802 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

摘要： A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

摘要翻译： SiC MOSFET具有在形成栅极绝缘膜之前对源极区域进行金属硅化退火时源极区域的电阻增加的对象，源极区域的金属硅化物层通过氧化处理（包括氮氧化处理）被氧化 ）形成栅极绝缘膜。 当在形成栅极绝缘膜界面层（氧化物膜）之前形成在SiC外延基板的表面上形成的金属硅化物层时，在金属硅化物层上形成用于金属硅化物的抗氧化膜， 可以通过在形成栅极绝缘膜界面层时的氧化处理来抑制金属硅化物层的氧化，并且可以降低源极区域的电阻而不降低沟道迁移率。

公开(公告)号：US20140239392A1

公开(公告)日：2014-08-28

申请号：US14239249

申请日：2012-06-07

申请人： Daisuke Matsumoto ,  Naoki Tega ,  Yasuhiro Shimamoto

发明人： Daisuke Matsumoto ,  Naoki Tega ,  Yasuhiro Shimamoto

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7838 ,  H01L27/0883 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66674 ,  H01L29/66712 ,  H01L29/7801 ,  H01L29/7802

摘要： A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106); a p body layer (103) which surrounds the source layer and has a channel region; an n−-type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p+ layer (109) which is disposed in the p body layer (103), extends to a portion below the n+ source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p+ layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.

摘要翻译： 提供了一种用于改善半导体器件（DMOSFET）的特性的技术。 半导体器件被配置为包括：设置在SiC衬底（106）的第一表面侧的上部的n型源极层（102）; 围绕源层并具有沟道区的p体层（103）; 与p体层（103）接触的n型漂移层（107）; 栅极电极，其经由栅极绝缘膜设置在所述沟道区域的上部; 并且设置在p体层（103）中的第一p +层（109）延伸到n +源极层（102）下方的部分，并且用作具有高于p的杂质浓度的掩埋半导体区域 身体层（103）。 以这种方式，由于第一p +层（109）形成在p体层（103）的中间，所以可以降低p体层（103）的扩散阻力。 因此，可以使寄生双极晶体管更难以导通。

公开(公告)号：US20120217513A1

公开(公告)日：2012-08-30

申请号：US13349430

申请日：2012-01-12

申请人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

发明人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

IPC分类号： H01L21/28 ,  H01L29/12

CPC分类号： H01L29/7802 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

摘要： A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

摘要翻译： SiC MOSFET具有在形成栅极绝缘膜之前对源极区域进行金属硅化退火时源极区域的电阻增加的对象，源极区域的金属硅化物层通过氧化处理（包括氮氧化处理）被氧化 ）形成栅极绝缘膜。 当在形成栅极绝缘膜界面层（氧化物膜）之前形成在SiC外延基板的表面上形成的金属硅化物层时，在金属硅化物层上形成用于金属硅化物的抗氧化膜， 可以通过在形成栅极绝缘膜界面层时的氧化处理来抑制金属硅化物层的氧化，并且可以降低源极区域的电阻而不降低沟道迁移率。