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    SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20120217513A1

    公开(公告)日：2012-08-30

    申请号：US13349430

    申请日：2012-01-12

    申请人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

    发明人： Naoki TEGA ,  Yasuhiro Shimamoto ,  Yuki Mori ,  Hirotaka Hamamura ,  Hiroyuki Okino ,  Digh Hisamoto

    IPC分类号： H01L21/28 ,  H01L29/12

    CPC分类号： H01L29/7802 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

    摘要： A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.

    摘要翻译： SiC MOSFET具有在形成栅极绝缘膜之前对源极区域进行金属硅化退火时源极区域的电阻增加的对象，源极区域的金属硅化物层通过氧化处理（包括氮氧化处理）被氧化 ）形成栅极绝缘膜。 当在形成栅极绝缘膜界面层（氧化物膜）之前形成在SiC外延基板的表面上形成的金属硅化物层时，在金属硅化物层上形成用于金属硅化物的抗氧化膜， 可以通过在形成栅极绝缘膜界面层时的氧化处理来抑制金属硅化物层的氧化，并且可以降低源极区域的电阻而不降低沟道迁移率。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
    半导体器件及其制造方法

    公开(公告)号：US20080048249A1

    公开(公告)日：2008-02-28

    申请号：US11773842

    申请日：2007-07-05

    申请人： NAOKI TEGA ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

    发明人： NAOKI TEGA ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

    IPC分类号： H01L29/792 ,  H01L21/336

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

    摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

    摘要翻译： 在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置 栅极绝缘膜（d> = 0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近连续平滑地接合。 通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。 因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

    Semiconductor device and method of manufacturing the same
    4.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US07709315B2

    公开(公告)日：2010-05-04

    申请号：US11773842

    申请日：2007-07-05

    申请人： Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

    发明人： Naoki Tega ,  Hiroshi Miki ,  Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833

    摘要： An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d≧0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.

    摘要翻译： 在选择栅极的底部附近的底部氧化物膜和氮化硅膜之间的界面位于硅衬底（p型阱）和硅衬底（p型阱）之间的界面的高度或更高的位置 栅极绝缘膜（d≥0）此外，栅极绝缘膜和底部氧化物膜在选择栅极的底部附近依次平滑地接合。 通过这种配置，减轻了在写入中注入到氮化硅膜中的电子分布中的定位，并且减少了通过热孔擦除而未被消除的电子。 因此，不仅可以减少在写入时未加电的电子的增加比例，还可以抑制在删除中阈值电压不降低到预定电压的问题。

    Non-volatile semiconductor memory device and method of manufacturing the same
    7.
    发明授权
    Non-volatile semiconductor memory device and method of manufacturing the same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08409949B2

    公开(公告)日：2013-04-02

    申请号：US12822157

    申请日：2010-06-23

    申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

    发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Toshiyuki Mine

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42328 ,  G11C16/3418 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7883

    摘要： Provided is a nonvolatile semiconductor memory device highly integrated and highly reliable. A plurality of memory cells are formed in a plurality of active regions sectioned by a plurality of isolations (silicon oxide films) extending in the Y direction and deeper than a well (p type semiconductor region). In each memory cell, a contact is provided in the well (p type semiconductor region) so as to penetrate through a source diffusion layer (n+ type semiconductor region), and the contact that electrically connects bit lines (metal wirings) and the source diffusion layer (n+ type semiconductor region) is also electrically connected to the well (p type semiconductor region).

    摘要翻译： 提供了高度集成且高度可靠的非易失性半导体存储器件。 多个存储单元形成在由在Y方向上延伸并且比阱（p型半导体区域）更深的多个隔离（氧化硅膜）分割的多个有源区域中。 在每个存储单元中，在阱（p型半导体区域）中提供接触以穿透源极扩散层（n +型半导体区域），并且将位线（金属布线）和源极扩散 层（n +型半导体区）也与阱（p型半导体区）电连接。

    Semiconductor device and manufacturing method of the same
    8.
    发明授权
    Semiconductor device and manufacturing method of the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US07935597B2

    公开(公告)日：2011-05-03

    申请号：US12912609

    申请日：2010-10-26

    申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

    发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

    摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

    摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一电介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER
    9.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICES WITH CHARGE INJECTION CORNER 有权
    带电荷注射角的非线性半导体存储器件

    公开(公告)号：US20080290401A1

    公开(公告)日：2008-11-27

    申请号：US12124143

    申请日：2008-05-20

    申请人： Kan YASUI ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

    发明人： Kan YASUI ,  Tetsuya Ishimaru ,  Digh Hisamoto ,  Yasuhiro Shimamoto

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/42344

    摘要： An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.

    摘要翻译： 在存储栅电极上设置有局部集中电场的角部的擦除方法，并且使用Fowler-Nordheim隧道操作将存储栅电极中的电荷注入栅极电介质中的电荷陷阱膜。 由于通过Fowler-Nordheim隧道可以减少擦除时的电流消耗，因此可以减少存储器模块的电源电路区域。 由于可以提高写入干扰电阻，所以可以通过采用更简单的存储器阵列配置来减少存储器阵列区域。 由于这两个效果，可以大大减少存储器模块的面积，从而可以降低制造成本。 此外，由于写入和擦除的电荷注入中心彼此一致，所以（编程和擦除）耐久性得到改善。

    Semiconductor device and manufacturing method thereof
    10.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US08385124B2

    公开(公告)日：2013-02-26

    申请号：US13075169

    申请日：2011-03-29

    申请人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

    发明人： Tsuyoshi Arigane ,  Digh Hisamoto ,  Yasuhiro Shimamoto ,  Yutaka Okuyama

    IPC分类号： G11C16/04

    CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/792

    摘要： The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

    摘要翻译： 半导体器件包括在半导体衬底的主表面中的非易失性存储单元。 非易失性存储单元在半导体衬底上具有第一绝缘膜，导电膜，第二绝缘膜，能够存储电荷的电荷存储膜，电荷存储膜上的第三绝缘膜，第一栅电极，第四绝缘膜 绝缘膜与从第一绝缘膜到前述第一栅电极的层叠膜接触;第五绝缘膜，与上述半导体衬底上的第一绝缘膜并置，形成在第五绝缘膜上的第二栅电极， 与第四绝缘膜的侧表面上的上述第一栅电极相邻，以及其间插入第一和第二栅电极的源/漏区。 导电膜和电荷存储膜形成为二维重叠。