公开(公告)号：US09368576B2

公开(公告)日：2016-06-14

申请号：US13612231

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7811 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813

摘要： Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

摘要翻译： 半导体器件的实施例及其形成方法包括提供具有顶表面，底表面，有源区和边缘区的半导体衬底，以及在半导体衬底的有源区中的第一沟槽中形成栅极结构。 在半导体衬底的边缘区域中的第二沟槽中形成端接结构。 端接结构具有面向有源区域和器件周边面侧。 该方法还包括形成第一和第二源极区域，该第一和第二源极区域邻近栅极结构的两侧形成在半导体衬底中。 第三源极区域形成在邻近端子结构的有源区域侧的半导体衬底中。 例如，半导体器件可以是沟槽金属氧化物半导体器件。

公开(公告)号：US08932928B2

公开(公告)日：2015-01-13

申请号：US14274773

申请日：2014-05-12

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/08

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20150162328A1

公开(公告)日：2015-06-11

申请号：US13983653

申请日：2011-02-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. De Fresart

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. De Fresart

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/265 ,  H01L21/823456 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

摘要翻译： 提供半导体器件结构和相关的制造方法。 示例性半导体器件结构（100）包括沟槽栅极结构（114），横向栅极结构（118），具有第一导电类型的体区（124），漏极区域（125）和第一和第二源极区域 128,130）具有第二导电类型。 第一和第二源极区域（128,130）形成在体区域（124）内。 所述漏极区域（125）与所述体区域（124）相邻，并且所述第一源极区域（128）与所述沟槽栅极结构（114）相邻，其中所述体区域（124）的第一部分设置在所述第一源极 区域（128）和漏极区域（125）相邻于沟槽栅极结构（114）。 身体区域（124）的第二部分设置在第二源极区域（130）和漏极区域（125）之间，并且横向栅极结构（118）被布置在身体区域（124）的第二部分上方。

公开(公告)号：US20130307060A1

公开(公告)日：2013-11-21

申请号：US13612231

申请日：2012-09-12

申请人： PEILIN WANG ,  Jingjing Chen ,  Edouard D. De Fresart

发明人： PEILIN WANG ,  Jingjing Chen ,  Edouard D. De Fresart

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813

摘要： Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

摘要翻译： 半导体器件的实施例及其形成方法包括提供具有顶表面，底表面，有源区和边缘区的半导体衬底，以及在半导体衬底的有源区中的第一沟槽中形成栅极结构。 在半导体衬底的边缘区域中的第二沟槽中形成端接结构。 端接结构具有面向有源区域和器件周边面侧。 该方法还包括形成第一和第二源极区域，该第一和第二源极区域邻近栅极结构的两侧形成在半导体衬底中。 第三源极区域形成在邻近端子结构的有源区域侧的半导体衬底中。 例如，半导体器件可以是沟槽金属氧化物半导体器件。

公开(公告)号：US20140342518A1

公开(公告)日：2014-11-20

申请号：US14274773

申请日：2014-05-12

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20130344667A1

公开(公告)日：2013-12-26

申请号：US13528375

申请日：2012-06-20

申请人： Ganming Qin ,  Edouard D. de Frésart ,  Peilin Wang ,  Pon S. Ku

发明人： Ganming Qin ,  Edouard D. de Frésart ,  Peilin Wang ,  Pon S. Ku

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/66727 ,  H01L29/66734

摘要： A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

摘要翻译： 使用成角度的注入（116,120）形成在形成自对准N +区域（123）的沟槽侧壁中的衬底（102,104）中来制造高电压垂直场效应晶体管器件（101） ）并且沿着升高的基底的上部区域。 利用形成在凹陷多晶硅层（114）上方的沟槽填充绝缘体层（124），将自对准P +体接触区域（128）注入升高的衬底中，而不会反向掺杂自对准的N +区域（123） 并且随后的凹陷蚀刻去除升高的衬底，留下自对准的N +源区（135-142）和P +体接触区（130-134）。

公开(公告)号：US20130299898A1

公开(公告)日：2013-11-14

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬垫内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US08030153B2

公开(公告)日：2011-10-04

申请号：US11932070

申请日：2007-10-31

申请人： Peilin Wang ,  Edouard D. de Frésart ,  Ganming Qin ,  Hongwei Zhou

发明人： Peilin Wang ,  Edouard D. de Frésart ,  Ganming Qin ,  Hongwei Zhou

IPC分类号： H01L21/8238

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719

摘要： A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

摘要翻译： 使用第一类型的半导体层（16）形成TMOS器件（10）。 第二类型的第一和第二区域（62,64）形成在半导体层中并且间隔开。 通过注入在半导体层中形成第三区域（68）。 第三区域在第一和第二掺杂区域之间并且与第一和第二掺杂区域接触，具有第二导电类型，并且比第一和第二掺杂区域重掺杂。 栅极堆叠（67）形成在第一掺杂区域的一部分，第二掺杂区域的一部分和第三掺杂区域上。 通过在形成栅叠层之后注入，第一类型的第四和第五区（98,100）分别形成在第一和第二掺杂区的内部。 与第一和第二区域具有相同导电类型的第三区域减小了米勒电容。

公开(公告)号：US08759909B2

公开(公告)日：2014-06-24

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US09293535B2

公开(公告)日：2016-03-22

申请号：US13610901

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7815

摘要： A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

摘要翻译： 功率MOSFET具有主FET（MFET）和嵌入式电流感测FET（SFET）。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道（IGR）耦合到SFET栅极流道。 在一个实施例中，n IGR（i = 1至n）将MFET（304）的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分，其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGR基本上没有源区。