公开(公告)号：US09178027B1

公开(公告)日：2015-11-03

申请号：US14457824

申请日：2014-08-12

申请人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

发明人： Moaniss Zitouni ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Michael F. Petras ,  Ganming Qin ,  Evgueniy N. Stefanov ,  Dragan Zupac

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L27/088 ,  H01L29/063 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/40 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41741 ,  H01L29/423 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7827

摘要： A device includes a semiconductor substrate having a surface, a trench in the semiconductor substrate extending vertically from the surface, a body region laterally adjacent the trench, spaced from the surface, having a first conductivity type, and in which a channel is formed during operation, a drift region between the body region and the surface, and having a second conductivity type, a gate structure disposed in the trench alongside the body region, recessed from the surface, and configured to receive a control voltage is applied to control formation of the channel, and a gate dielectric layer disposed along a sidewall of the trench between the gate structure and the body region. The gate structure and the gate dielectric layer have a substantial vertical overlap with the drift region such that electric field magnitudes in the drift region are reduced through application of the control voltage.

摘要翻译： 一种器件包括具有表面的半导体衬底，半导体衬底中的从表面垂直延伸的沟槽，与沟槽横向相邻的主体区域，与表面间隔开，具有第一导电类型，并且其中在操作期间形成沟道 ，在身体区域和表面之间的漂移区域，并且具有第二导电类型，施加设置在与身体区域相邻的沟槽中的栅极结构，从表面凹陷并被配置为接收控制电压以控制形成 沟道，以及沿栅极结构和主体区域之间的沟槽的侧壁设置的栅极电介质层。 栅极结构和栅极电介质层与漂移区域具有实质的垂直重叠，使得通过施加控制电压来减小漂移区域中的电场幅度。

公开(公告)号：US20150162328A1

公开(公告)日：2015-06-11

申请号：US13983653

申请日：2011-02-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. De Fresart

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. De Fresart

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L27/088 ,  H01L21/265 ,  H01L21/823456 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7827

摘要： Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure (100) includes a trench gate structure (114), a lateral gate structure (118), a body region (124) having a first conductivity type, a drain region (125) and first and second source regions (128, 130) having a second conductivity type. The first and second source regions (128, 130) are formed within the body region (124). The drain region (125) is adjacent to the body region (124) and the first source region (128) is adjacent to the trench gate structure (114), wherein a first portion of the body region (124) disposed between the first source region (128) and the drain region (125) is adjacent to the trench gate structure (114). A second portion of the body region (124) is disposed between the second source region (130) and the drain region (125), and the lateral gate structure (118) is disposed overlying the second portion of the body region (124).

摘要翻译： 提供半导体器件结构和相关的制造方法。 示例性半导体器件结构（100）包括沟槽栅极结构（114），横向栅极结构（118），具有第一导电类型的体区（124），漏极区域（125）和第一和第二源极区域 128,130）具有第二导电类型。 第一和第二源极区域（128,130）形成在体区域（124）内。 所述漏极区域（125）与所述体区域（124）相邻，并且所述第一源极区域（128）与所述沟槽栅极结构（114）相邻，其中所述体区域（124）的第一部分设置在所述第一源极 区域（128）和漏极区域（125）相邻于沟槽栅极结构（114）。 身体区域（124）的第二部分设置在第二源极区域（130）和漏极区域（125）之间，并且横向栅极结构（118）被布置在身体区域（124）的第二部分上方。

公开(公告)号：US20130307060A1

公开(公告)日：2013-11-21

申请号：US13612231

申请日：2012-09-12

申请人： PEILIN WANG ,  Jingjing Chen ,  Edouard D. De Fresart

发明人： PEILIN WANG ,  Jingjing Chen ,  Edouard D. De Fresart

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7813

摘要： Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

摘要翻译： 半导体器件的实施例及其形成方法包括提供具有顶表面，底表面，有源区和边缘区的半导体衬底，以及在半导体衬底的有源区中的第一沟槽中形成栅极结构。 在半导体衬底的边缘区域中的第二沟槽中形成端接结构。 端接结构具有面向有源区域和器件周边面侧。 该方法还包括形成第一和第二源极区域，该第一和第二源极区域邻近栅极结构的两侧形成在半导体衬底中。 第三源极区域形成在邻近端子结构的有源区域侧的半导体衬底中。 例如，半导体器件可以是沟槽金属氧化物半导体器件。

公开(公告)号：US07074681B2

公开(公告)日：2006-07-11

申请号：US10614553

申请日：2003-07-07

申请人： Edouard D. de Fresart ,  Patrice Parris ,  Richard Joseph De Souza

发明人： Edouard D. de Fresart ,  Patrice Parris ,  Richard Joseph De Souza

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/66689 ,  H01L29/7834 ,  H01L29/812 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component includes a substrate (110) having a surface, a channel region (120, 220) located in the substrate, a non-electrically conductive region (130) substantially located below a substantially planar plane defined by the surface of the substrate, a drift region (140, 240) located in the substrate and between the channel region and the non-electrically conductive region, and an electrically floating region (150, 350, 450, 550) located in the substrate and contiguous with the non-electrically conductive region.

摘要翻译： 半导体部件包括具有表面的衬底（110），位于衬底中的沟道区（120,220），基本上位于由衬底的表面限定的基本上平面的下方的非导电区（130） 位于所述衬底中且位于所述沟道区和所述非导电区之间的漂移区（140,240）以及位于所述衬底中且与所述非导电区相邻的电浮置区（150,350,450,550） 导电区域。

公开(公告)号：US08759909B2

公开(公告)日：2014-06-24

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20110275187A1

公开(公告)日：2011-11-10

申请号：US12777066

申请日：2010-05-10

申请人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

发明人： Jingjing Chen ,  Ganming Qin ,  Edouard D. de Fresart ,  Pon Sung Ku

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/42376 ,  H01L29/66734

摘要： A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

摘要翻译： 使用一种方法来形成垂直MOS晶体管。 该方法利用半导体层。 在半导体层中蚀刻开口。 栅极电介质形成在开口中，其具有延伸到第一半导体层的顶表面的垂直部分。 栅极形成在开口中，其主要部分横向邻近栅极电介质的垂直部分，并且悬垂部分横向延伸越过栅极电介质的垂直部分。 执行注入以在半导体层的顶表面处形成源极区域，同时存在突出部分。

公开(公告)号：US6084268A

公开(公告)日：2000-07-04

申请号：US962725

申请日：1997-11-03

申请人： Edouard D. de Fresart ,  Pak Tam ,  Hak-Yam Tsoi

发明人： Edouard D. de Fresart ,  Pak Tam ,  Hak-Yam Tsoi

IPC分类号： H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/7813 ,  H01L29/7802 ,  H01L29/0847 ,  H01L29/42368

摘要： A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

摘要翻译： 功率MOSFET器件（40）包括在更轻掺杂的半导体层（42）中形成的一个或多个局部的掺杂区域（61,62,63）。 一个或多个局部的掺杂区域（61,62,63）降低了器件的源极区域（47,48）和漏极区域（41）之间的固有电阻。 一个或多个局部的掺杂区域（61,62,63）与主体区域（44,46）间隔开，以避免不利地影响器件击穿电压。 在替代实施例中，结合凹槽（122）或沟槽（152）设计以减少JFET电阻（34）。 在另一实施例中，并入具有厚部分（77,97,128,158）和薄部分（76,126,156）的栅介质层，以增强开关特性和/或击穿电压。

公开(公告)号：US5273930A

公开(公告)日：1993-12-28

申请号：US940402

申请日：1992-09-03

申请人： John W. Steele ,  Edouard D. de Fresart

发明人： John W. Steele ,  Edouard D. de Fresart

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/737 ,  H01L21/203

CPC分类号： H01L29/66242 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/7378

摘要： A method of forming a silicon-germanium epitaxial layer using dichlorosilane as a silicon source gas. A semiconductor seed layer (15) is formed on a portion of a semiconductor layer (12) and on a portion of a layer of dielectric material (13). The semiconductor seed layer (15) provides nucleation sites for a Si-Ge epitaxial alloy layer (16). The epitaxial film (16) is formed on the semiconductor seed layer (15). Both the semiconductor seed layer (15) and the Si-Ge epitaxial film (16) are formed at a system growth pressure between approximately 25 and 760 millimeters of mercury and a temperature below approximately 900.degree. C. The semiconductor seed layer (15) and the Si-Ge epitaxial film (16) permit fabrication of a heterostructure semiconductor integrated circuit (10), thereby allowing the exploitation of band-gap engineering techniques.

摘要翻译： 使用二氯硅烷作为硅源气体形成硅 - 锗外延层的方法。 在半导体层（12）的一部分和电介质材料层（13）的一部分上形成半导体种子层（15）。 半导体晶种层（15）为Si-Ge外延合金层（16）提供成核位置。 外延膜（16）形成在半导体种子层（15）上。 半导体种子层（15）和Si-Ge外延膜（16）都以约25和760毫米汞柱之间的系统生长压力和低于约900℃的温度形成。半导体种子层（15）和 Si-Ge外延膜（16）允许制造异质结构半导体集成电路（10），从而允许利用带隙工程技术。

公开(公告)号：US20140342518A1

公开(公告)日：2014-11-20

申请号：US14274773

申请日：2014-05-12

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20130299898A1

公开(公告)日：2013-11-14

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬垫内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。