公开(公告)号：US20110003444A1

公开(公告)日：2011-01-06

申请号：US12883096

申请日：2010-09-15

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US08021957B2

公开(公告)日：2011-09-20

申请号：US12883096

申请日：2010-09-15

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07843011B2

公开(公告)日：2010-11-30

申请号：US11669794

申请日：2007-01-31

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US20080179679A1

公开(公告)日：2008-07-31

申请号：US11669794

申请日：2007-01-31

申请人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

发明人： Paul A. Grudowski ,  Venkat R. Kolagunta ,  Mehul D. Shroff

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/3143 ,  H01L21/3185 ,  H01L21/76264 ,  H01L21/84 ,  H01L29/78 ,  H01L29/7843

摘要： An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

摘要翻译： 电子设备可以包括场隔离区域和具有第一应变的第一绝缘层，并且具有从顶视图完全位于场隔离区域内的部分。 电子器件还可以包括具有不同于第一应变的第二应变并且包括开口的第二绝缘层。 从顶视图，第一绝缘层的部分可以位于第二绝缘层的开口内。 在一个实施例中，场隔离区域可以包括虚拟结构，并且第一绝缘层的部分可以覆盖虚拟结构。 形成电子器件的过程可以包括形成绝缘层的岛部，其中从顶视图看，岛部完全位于场隔离区内。

公开(公告)号：US07511360B2

公开(公告)日：2009-03-31

申请号：US11300091

申请日：2005-12-14

申请人： Mehul D. Shroff ,  Paul A. Grudowski

发明人： Mehul D. Shroff ,  Paul A. Grudowski

IPC分类号： H01L29/72

CPC分类号： H01L29/7843 ,  H01L21/3185 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： N channel and P channel transistors are enhanced by applying stressor layers of tensile and compressive, respectively, over them. A previously unknown problem was discovered concerning the two stressor layers, which both may conveniently be nitride but made somewhat differently. The two stressors have different etch rates which results in deleterious effects when etching a contact hole at the interface between the two stressors. A contact to a gate is often preferably half way between N and P channel transistors which is also the seemingly best location for the border between the two stressor layers. The contact etch at the border can result in pitting of the underlying gate structure or in residual nitride in the contact hole. Therefore, it has been found beneficial to ensure that each contact is at least some predetermined distance from the stressor of the opposite type from the one the contact is passing through.

摘要翻译： 通过在其上分别施加拉伸和压缩的应力层来增强N沟道和P沟道晶体管。 发现关于两个应力层的以前未知的问题，这两个应力层都可以方便地是氮化的，但是略有不同。 两个应力源具有不同的蚀刻速率，这在蚀刻两个应激物之间的界面处的接触孔时会产生有害影响。 与栅极的接触通常优选在N沟道晶体管和P沟道晶体管之间，这也是两个应力层之间边界的看似最佳位置。 在边界处的接触蚀刻可导致底层栅极结构或接触孔中的残余氮化物的点蚀。 因此，已经发现有益的是确保每个接触件与来自接触件通过的相反类型的应力器至少一定的距离。

公开(公告)号：US07491630B2

公开(公告)日：2009-02-17

申请号：US11375768

申请日：2006-03-15

申请人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

发明人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

IPC分类号： H01L21/04

CPC分类号： H01L21/82345 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462

摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。

公开(公告)号：US09685405B2

公开(公告)日：2017-06-20

申请号：US13907497

申请日：2013-05-31

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L49/02

CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

公开(公告)号：US20150348898A1

公开(公告)日：2015-12-03

申请号：US14292886

申请日：2014-05-31

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  G06F17/50

CPC分类号： H01L23/5283 ,  G06F17/5077 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for selecting locations within an integrated circuit device for placing stressors to manage electromigration failures includes calculating an electric current for an interconnect within the integrated circuit device and determining an electromigration stress profile for the interconnect based on the electric current. The method further includes determining an area on the interconnect for placing a stressor to alter the electromigration stress profile for the interconnect.

摘要翻译： 用于选择集成电路装置中用于放置应力源以管理电迁移故障的位置的方法包括计算集成电路装置内的互连的电流，并基于电流确定互连的电迁移应力分布。 该方法还包括确定互连上的区域以放置应力源以改变互连的电迁移应力分布。

公开(公告)号：US20150279854A1

公开(公告)日：2015-10-01

申请号：US14228678

申请日：2014-03-28

申请人： MARK D. HALL ,  Mehul D. Shroff

发明人： MARK D. HALL ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

公开(公告)号：US20150234961A1

公开(公告)日：2015-08-20

申请号：US14558694

申请日：2014-12-02

申请人： Zhichen Zhang ,  Xavier Hours ,  Mehul D. Shroff ,  Chuanzheng Wang ,  Qilin Zhang

发明人： Zhichen Zhang ,  Xavier Hours ,  Mehul D. Shroff ,  Chuanzheng Wang ,  Qilin Zhang

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/76

摘要： A method for integrated circuit reliability aging simulation includes dividing a target time period into N stages including a first stage and a second stage; obtaining first parameter values of a reliability model for the first stage; performing a first simulation on the circuit based on the reliability model and the first parameter values to obtain first aging results; obtaining second parameter values of the reliability model for the second stage; and performing a second simulation on the circuit based on the reliability model and the second parameter values to obtain second aging results.

摘要翻译： 一种用于集成电路可靠性老化模拟的方法，包括将目标时间段划分为包括第一阶段和第二阶段的N个阶段; 获得第一阶段的可靠性模型的第一参数值; 基于可靠性模型和第一参数值在电路上执行第一模拟以获得第一老化结果; 获得第二阶段的可靠性模型的第二参数值; 以及基于所述可靠性模型和所述第二参数值在所述电路上执行第二仿真以获得第二老化结果。