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1.发明授权Method of forming a semiconductor device with multiple tensile stressor layers 有权用多个拉伸应力层形成半导体器件的方法公开(公告)号：US07678698B2
公开(公告)日：2010-03-16
申请号：US11744581
申请日：2007-05-04
IPC分类号： H01L21/44
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L21/3185 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二张应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。
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公开(公告)号：US20080272411A1
公开(公告)日：2008-11-06
申请号：US11744581
申请日：2007-05-04
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/7843 , H01L21/268 , H01L21/3105 , H01L21/3185 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.
摘要翻译： 半导体器件具有至少两个用UV辐射固化的拉伸应力层。 在第一应力层之后形成第二拉伸应力层。 在一些实例中，拉伸应力层包括氮化硅和氢。 在一些实例中，第二拉伸应力层由于固化而比第一拉伸应力层具有更大的收缩率。 在一种形式中，固化后的第二拉伸应力层比第一拉伸应力层具有更大的拉伸应力。 拉伸应力层用于改善N沟道晶体管中的载流子迁移率，从而提高晶体管性能。 在一种形式中，提供单组上覆的拉伸应力层，每层越来越厚，并且在固化之前具有越来越多的氢。 在其它实施方案中，形成多个重叠的基团，每个基团具有相似的重复深度和氢分布。
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公开(公告)号：US20080173908A1
公开(公告)日：2008-07-24
申请号：US11655461
申请日：2007-01-19
IPC分类号： H01L29/78 , H01L21/3105 , H01L21/8238
CPC分类号： H01L21/02348 , H01L21/0217 , H01L21/02274 , H01L21/02351 , H01L21/3105 , H01L21/3185 , H01L21/823807 , H01L29/7843
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (131) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (133) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译： 提供了制造半导体器件的方法，其包括（a）提供配备有栅极和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（131），所述第一应力源材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（133），所述第二应力源材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。
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公开(公告)号：US20110210401A1
公开(公告)日：2011-09-01
申请号：US12713262
申请日：2010-02-26
IPC分类号： H01L27/092 , H01L29/78
CPC分类号： H01L21/823807 , H01L21/0214 , H01L21/0217 , H01L21/02274 , H01L27/092 , H01L29/78 , H01L29/7843
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon- nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。
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公开(公告)号：US07700499B2
公开(公告)日：2010-04-20
申请号：US12008607
申请日：2008-01-11
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。
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公开(公告)号：US20080173986A1
公开(公告)日：2008-07-24
申请号：US12008607
申请日：2008-01-11
CPC分类号： H01L21/823807 , H01L29/78 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method for making a semiconductor device is provided which comprises (a) providing a semiconductor structure equipped with a gate (209) and a channel region, said channel region being associated with the gate; (b) depositing a first sub-layer (231) of a first stressor material over the semiconductor structure, said first stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; (c) curing the first stressor material through exposure to a radiation source; (d) depositing a second sub-layer (233) of a second stressor material over the first sub-layer, said second stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure; and (e) curing the second sub-layer of stressor material through exposure to a radiation source.
摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供配备有栅极（209）和沟道区域的半导体结构，所述沟道区域与栅极相关联; （b）在半导体结构上沉积第一应力源材料的第一子层（231），所述第一应力材料含有硅 - 氮键并向半导体结构施加拉伸应力; （c）通过暴露于辐射源固化第一应激物材料; （d）在所述第一子层上沉积第二应力源材料的第二子层（233），所述第二应力材料含有硅 - 氮键并向所述半导体结构施加拉伸应力; 和（e）通过暴露于辐射源固化应力源材料的第二子层。
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公开(公告)号：US07402472B2
公开(公告)日：2008-07-22
申请号：US11067257
申请日：2005-02-25
IPC分类号： H01L21/336
CPC分类号： H01L21/02329 , H01L21/02181 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3141 , H01L21/3144 , H01L21/3185 , H01L29/4908 , H01L29/511 , H01L29/6659 , H01L29/7833
摘要： A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.
摘要翻译： 用氮化步骤和退火处理栅极电介质。 之后，进行另外的氮化步骤和退火。 第二次氮化和退火导致栅极漏电流密度与最终形成的晶体管的电流驱动之间的关系得到改善。
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公开(公告)号：US07767588B2
公开(公告)日：2010-08-03
申请号：US11364128
申请日：2006-02-28
申请人： Tien Ying Luo , Rajesh A. Rao
发明人： Tien Ying Luo , Rajesh A. Rao
IPC分类号： H01L21/31 , H01L21/461
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/02164 , H01L21/02271 , H01L21/02304 , H01L21/02337 , H01L21/31612 , H01L29/42332 , H01L29/7883 , H01L29/7885
摘要： An insulating layer formed by deposition is annealed in the presence of radical oxygen to reduce bond defects. A substrate is provided. An oxide layer is deposited overlying the substrate. The oxide layer has a plurality of bond defects. The oxide layer is annealed in the presence of radical oxygen to modify a substantial portion of the plurality of bond defects by using oxygen atoms. The anneal, in one form, is an in-situ steam generation (ISSG) anneal. In one form, the insulating layer overlies a layer of charge storage material, such as nanoclusters, that form a gate structure of a semiconductor storage device. The ISSG anneal repairs bond defects by oxidizing defective silicon bonds in the oxide layer when the oxide layer is silicon dioxide.
摘要翻译： 通过沉积形成的绝缘层在自由基氧的存在下退火以减少键合缺陷。 提供基板。 沉积在衬底上的氧化物层。 氧化物层具有多个键合缺陷。 氧化层在自由基氧的存在下进行退火，通过使用氧原子来修饰多个键缺陷的大部分。 一种形式的退火是原位蒸汽发生（ISSG）退火。 在一种形式中，绝缘层覆盖形成半导体存储装置的栅极结构的诸如纳米团簇的电荷存储材料层。 当氧化物层是二氧化硅时，ISSG退火通过氧化氧化物层中的有缺陷的硅键来修复接合缺陷。
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公开(公告)号：US20080026526A1
公开(公告)日：2008-01-31
申请号：US11459837
申请日：2006-07-25
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L21/28273 , H01L21/28282 , H01L21/32134 , H01L27/11526 , H01L27/11531 , H01L27/11573 , Y10S977/774 , Y10S977/779 , Y10S977/78 , Y10S977/943
摘要： A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.
摘要翻译： 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 在半导体层上形成第一电介质层。 在第一电介质层上进行等离子体氮化。 在第一部分上形成第一多个纳米团簇，并在第二部分上形成第二多个纳米团簇。 第二组纳米团簇被去除。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。
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公开(公告)号：USRE45955E1
公开(公告)日：2016-03-29
申请号：US14452736
申请日：2014-08-06
申请人： Tien Ying Luo , Gauri V. Karve , Daniel K. Tekleab
发明人： Tien Ying Luo , Gauri V. Karve , Daniel K. Tekleab
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/4958 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).
摘要翻译： 描述了用于在PMOS器件中具有硅锗沟道层（21）的单个衬底（15）上集成双栅极氧化物（DGO）晶体管器件（50,52）和核心晶体管器件（51,53）的方法和装置 区域（112,113），其中每个DGO晶体管器件（50,52）包括金属栅极（25），由第二相对较高的高k金属氧化物层（24）形成的上部栅极氧化区域（60,84） ）和由第一相对较低的高k层（22）形成的下栅极氧化物区域（58,84），并且其中每个核心晶体管器件（51,53）包括金属栅极（25）和芯栅极电介质 仅由第二相对较高的高k金属氧化物层（24）形成的层（72,98）。
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