公开(公告)号：US5515012A

公开(公告)日：1996-05-07

申请号：US442850

申请日：1995-05-17

申请人： Bharat Bhushan ,  Christopher G. Arcus ,  Paul D. Ta

发明人： Bharat Bhushan ,  Christopher G. Arcus ,  Paul D. Ta

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

摘要翻译： 锁相环电路的环形多级VCO包括两个或更多个差分放大器级。 锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和连接到第二二极管连接的MOS晶体管M2 其漏极端子。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到锁相环的电压控制输入端。

公开(公告)号：US5523723A

公开(公告)日：1996-06-04

申请号：US443131

申请日：1995-05-17

申请人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

发明人： Christopher G. Arcus ,  Bharat Bhushan ,  Paul D. Ta

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/099 ,  H03B5/04

CPC分类号： H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

摘要： A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

摘要翻译： 锁相环电路的环形多级VCO包括两个或更多个差分放大器级。 锁相环包括连接在控制电压端子和电压 - 电流转换器级之间的低通滤波器，其包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和与其连接的二极管连接的MOS晶体管M2 漏极端子。 电流源MOS晶体管M8具有连接到第一MOS晶体管M1的漏极的栅极端子，使得晶体管M8镜像晶体管M1的电流。 二极管连接的晶体管M9的栅极端子和其漏极端子连接在一起，并且还连接到晶体管M8的漏极端子。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10的栅极端子连接到第一MOS晶体管M1的漏极，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子为IN端子，MOS晶体管M5的栅极端子为IN端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的栅极端子连接到晶体管M9的漏极端子。

公开(公告)号：US09606926B2

公开(公告)日：2017-03-28

申请号：US14556143

申请日：2014-11-29

申请人： Vakul Garg ,  Bharat Bhushan

发明人： Vakul Garg ,  Bharat Bhushan

IPC分类号： G06F12/00 ,  G06F12/0862

CPC分类号： G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6028

摘要： A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

公开(公告)号：US20160154737A1

公开(公告)日：2016-06-02

申请号：US14556143

申请日：2014-11-29

申请人： Vakul Garg ,  Bharat Bhushan

发明人： Vakul Garg ,  Bharat Bhushan

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6028

摘要： A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

摘要翻译： 用于将数据帧从系统存储器预取入高速缓冲存储器的系统包括处理器，队列管理器和预取管理器。 处理器发出与数据帧相关联的解除队列请求。 队列管理器接收去队列请求，识别与数据帧相关联的帧描述符，并生成预取提示信号。 预取管理器接收预取提示信号并产生预取信号，并使缓存存储器能够预取数据帧。 随后，队列管理器对帧描述符进行排队。 处理器接收帧描述符并从高速缓冲存储器读取数据帧。

公开(公告)号：US07886238B1

公开(公告)日：2011-02-08

申请号：US11564223

申请日：2006-11-28

申请人： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srinivas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

发明人： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srinivas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

摘要翻译： 公开了基于产量分析优化布局的系统和方法。 该方法包括生成具有两层或更多层导线互连的集成电路布局，以形成网段，并且具有一个或多个通孔接触层以将导线互连中的网段耦合在一起。 该方法还包括对集成电路布局中的网段执行收益率分析，并使用多个不透明度级别对收益率分析的视觉描绘来显示净段以反映集成电路布局中的网段的收益率。

公开(公告)号：US07600208B1

公开(公告)日：2009-10-06

申请号：US11669872

申请日：2007-01-31

申请人： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srivinas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

发明人： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srivinas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G06F17/5068

摘要： Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

摘要翻译： 公开了用于在集成电路中自动放置去耦电容器以补偿电网中可能出现的电压降的方法，系统和装置。 在本发明的一个实施例中，该方法包括生成集成电路设计的一个或多个区域，每个区域具有一个或多个单元，通过分析集成电路设计的每个单元来确定集成电路设计的每个区域中所需的去耦电容量 并且向该区域添加足够的去耦电容器单元以补偿潜在的电压降。

公开(公告)号：US07023220B2

公开(公告)日：2006-04-04

申请号：US10967930

申请日：2004-10-19

申请人： Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

发明人： Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

IPC分类号： G01R27/26

CPC分类号： G01Q60/46 ,  G01R27/2605 ,  Y10S977/866

摘要： A method for measuring nm-scale tip-sample capacitance including (a) measuring a cantilever deflection and a change in probe-sample capacitance relative to a reference level as a function of a probe assembly height; (b) fitting out-of-contact data to a function; (c) subtracting the function from capacitance data to get a residual capacitance as a function of the probe assembly height; and (d) determining the residual capacitance at a z-position where the cantilever deflection is zero.

摘要翻译： 一种用于测量nm尺度尖端样本电容的方法，包括（a）测量悬臂偏转和相对于参考水平的探针样品电容的变化，作为探针组件高度的函数; （b）将不合格数据拟合到一个功能上; （c）从电容数据中减去该功能，以获得作为探头组件高度的函数的残余电容; 和（d）确定悬臂偏转为零的z位置处的残余电容。

公开(公告)号：US06754689B2

公开(公告)日：2004-06-22

申请号：US09745697

申请日：2000-12-22

申请人： Bharat Bhushan ,  Edward Grochowski ,  John Crawford

发明人： Bharat Bhushan ,  Edward Grochowski ,  John Crawford

IPC分类号： G06F750

CPC分类号： G06F7/50 ,  G06F7/4824

摘要： A method and apparatus is disclosed that uses an arithmetic circuit for adding numbers represented in redundant form to subtract numbers received in redundant form, including numbers received from a bypass circuit. The method includes generating a complemented redundant form of at least one number supplied to the arithmetic circuit in redundant form. It also includes providing an adjustment input to the arithmetic circuit to augment a result produced through the arithmetic circuit to generate a valid outcome in redundant form of a subtraction operation. A carry-save adder structure is used in one preferred embodiment of the current invention to perform a subtraction operation A−B, where B is a number represented by one of its valid carry-sum redundant representations. In order to perform the subtraction operation, each of the carry bits and each of the sum bits in a redundant representation of B are complemented and supplied to the carry-save adder. Then a result is corrected by adding an adjustment of three. This adjustment value is incorporated into the result through the carry-save adder circuit. Thus the circuit produces a valid redundant representation for the subtraction operation A−B.

摘要翻译： 公开了一种方法和装置，其使用运算电路来添加以冗余形式表示的数字，以减去以冗余形式接收的数字，包括从旁路电路接收的数字。 该方法包括以冗余的形式生成提供给运算电路的至少一个数的补码冗余形式。 它还包括向算术电路提供调整输入以增加通过算术电路产生的结果，以产生冗余形式的减法运算来产生有效结果。在本发明的一个优选实施例中使用进位保存加法器结构 执行减法运算AB，其中B是由其有效进位和冗余表示之一表示的数。 为了执行减法运算，B的冗余表示中的每个进位位和每个和位被补码并提供给进位存储加法器。 然后通过添加三个调整来校正结果。 该调整值通过进位保存加法器电路并入结果。 因此，该电路产生用于减法运算A-B的有效冗余表示。

公开(公告)号：US06724199B1

公开(公告)日：2004-04-20

申请号：US10165690

申请日：2002-06-07

申请人： Bharat Bhushan ,  Christopher D. Hahm

发明人： Bharat Bhushan ,  Christopher D. Hahm

IPC分类号： G01R2726

CPC分类号： H02J1/10 ,  G01Q10/06 ,  G11B2005/001

摘要： Capacitive film thickness measurement devices and measurement systems used in machines or instruments. A capacitance measurement device and technique useful in determining lubricant film thickness on substrates such as magnetic thin-film rigid disks. Variations in lubricant thickness on the Angstrom scale or less may be measured quickly and nondestructively.

摘要翻译： 用于机器或仪器的电容薄膜厚度测量装置和测量系统。 一种用于确定诸如磁性薄膜刚性盘的衬底上的润滑剂膜厚度的电容测量装置和技术。 润滑剂厚度的变化在埃刻度或更小可以快速和非破坏性地测量。

公开(公告)号：US6007896A

公开(公告)日：1999-12-28

申请号：US55615

申请日：1998-04-06

申请人： Bharat Bhushan

发明人： Bharat Bhushan

IPC分类号： G11B5/187 ,  G11B5/72 ,  G11B5/73 ,  G11B5/78 ,  G11B5/82 ,  G11B5/84 ,  G11B3/70

CPC分类号： G11B5/7315 ,  G11B5/1871 ,  G11B5/72 ,  G11B5/78 ,  G11B5/82 ,  G11B5/8404 ,  Y10S428/90 ,  Y10T428/24355

摘要： A low friction non-gaussian surface is disclosed which has a positive skewness value and a kurtosis value of three or greater which minimizes static and kinetic friction and resultant wear in any instance of at least two surfaces in moving contact, including machine and computer components, magnetic media, and read/write heads which contact magnetic media. In a preferred embodiment, a magnetic media having an optimal non-gaussian surface roughness and method of surface parameter selection utilizes non-gaussian probability density functions in a contact model which accounts for the effects of roughness distribution and liquid film meniscus forces to determine optimum skewness and kurtosis values which minimize static and kinetic friction. The invention provides a magnetic media or other article of manufacture with a surface which has a positive skewness value and as high a kurtosis value as possible which minimizes or reduces static and kinetic friction and wear upon contact with another surface which may also be surface configured in accordance with the invention.

摘要翻译： 公开了一种低摩擦非高斯表面，其具有三个或更大的正偏度值和三次峰值，其最大程度地减少静电和动摩擦以及在移动接触中的至少两个表面（包括机器和计算机部件）的任何情况下的合成磨损， 磁性介质以及与磁性介质接触的读/写头。 在优选实施例中，具有最佳非高斯表面粗糙度的磁介质和表面参数选择方法在接触模型中使用非高斯概率密度函数，其考虑了粗糙度分布和液膜弯月面力的影响以确定最佳偏度 和峰度值，其最小化静态和动摩擦。 本发明提供一种具有表面的磁性介质或其它制品，该表面具有正的偏斜度值和尽可能高的峰度值，其可以在与另一表面接触时最小化或减少静态和动力学摩擦和磨损，所述另一表面也可以表面配置 根据本发明。