Array column integrator
    1.
    发明授权
    Array column integrator 有权
    阵列列积分器

    公开(公告)号:US08432149B2

    公开(公告)日:2013-04-30

    申请号:US13174465

    申请日:2011-06-30

    申请人: Peter Levine

    发明人: Peter Levine

    IPC分类号: G01R27/00

    摘要: The described embodiments may provide a chemical detection circuit with an improved signal-to-noise ration. The chemical detection circuit may include a current source, a chemical detection pixel, an amplifier and a capacitor. The chemical detection pixel may comprise a chemical-sensitive transistor that may have a first and second terminals and a row-select switch coupled between the current source and chemically-sensitive transistor. The amplifier may have a first input and a second input, with the first input coupled to an output of the chemically-sensitive transistor via a switch and the second input coupled to an offset voltage line. The capacitor may be coupled between an output of the amplifier and the first input of the amplifier. The capacitor and amplifier may form an integrator and may be shared by a column of chemical detection pixels.

    摘要翻译: 所描述的实施例可以提供具有改进的信噪比的化学检测电路。 化学检测电路可以包括电流源,化学检测像素,放大器和电容器。 化学检测像素可以包括可以具有第一和第二端子的化学敏感晶体管和耦合在电流源和化学敏感晶体管之间的行选择开关。 放大器可以具有第一输入和第二输入,其中第一输入经由开关耦合到化学敏感晶体管的输出,并且第二输入耦合到偏移电压线。 电容器可以耦合在放大器的输出端和放大器的第一输入端之间。 电容器和放大器可以形成积分器,并且可以被一列化学检测像素共享。

    ARRAY CONFIGURATION AND READOUT SCHEME
    2.
    发明申请
    ARRAY CONFIGURATION AND READOUT SCHEME 有权
    阵列配置和读取方案

    公开(公告)号:US20120022795A1

    公开(公告)日:2012-01-26

    申请号:US13174514

    申请日:2011-06-30

    IPC分类号: G06F19/00 H01L29/66

    摘要: The described embodiments may provide a chemical detection circuit that may comprise a plurality of first output circuits at a first side and a plurality of second output circuits at a second side of the chemical detection circuit. The chemical detection circuit may further comprise a plurality of tiles of pixels each placed between respective pairs of first and second output circuits. Each tile may include four quadrants of pixels. Each quadrant may have columns with designated first columns interleaved with second columns. Each first column may be coupled to a respective first output circuit in first and second quadrants, and to a respective second output circuit in third and fourth quadrants. Each second column may be coupled to a respective second output circuit in first and second quadrants, and to a respective first output circuit in third and fourth quadrants.

    摘要翻译: 所描述的实施例可以提供化学检测电路,其可以包括在第一侧的多个第一输出电路和在化学检测电路的第二侧的多个第二输出电路。 化学检测电路还可以包括多个像素瓦片,每个瓷砖分别放置在相应的第一和第二输出电路对之间。 每个瓦片可以包括四个像素象限。 每个象限可以具有与第二列交错的指定的第一列的列。 每个第一列可以耦合到第一和第二象限中的相应的第一输出电路,以及耦合到第三和第四象限中的相应的第二输出电路。 每个第二列可以耦合到第一和第二象限中的相应的第二输出电路,以及耦合到第三和第四象限中的相应的第一输出电路。

    Method and Apparatus for Reducing Smear in Back-Illuminated Imaging Sensors
    3.
    发明申请
    Method and Apparatus for Reducing Smear in Back-Illuminated Imaging Sensors 有权
    用于减少后照射成像传感器中的涂片的方法和装置

    公开(公告)号:US20080061390A1

    公开(公告)日:2008-03-13

    申请号:US11844775

    申请日:2007-08-24

    IPC分类号: H01L31/0232 H01L31/18

    摘要: A method for fabricating a back-illuminated semiconductor imaging device and resulting imaging device is disclosed, which includes the steps providing a substrate having a front surface and a back surface; growing an epitaxial layer substantially overlying the front surface of the substrate; forming at least one barrier layer substantially within the epitaxial layer; fabricating at least one imaging structure overlying and extending into the epitaxial layer, the imaging structure at least one charge transfer region, the at least one barrier layer substantially underlying the at least one charge transfer region, wherein light incident on the back surface of the substrate generates charge carriers which are diverted away from the at least one charge transfer region by the at least one barrier layer. At least a portion of the epitaxial layer is grown using an epitaxial lateral overgrowth technique. The barrier layer can be a high energy implant formed substantially within the epitaxial layer, an optical shield made of an optically opaque material surrounded by oxide on all sides, or a combination of both. The imaging structure can be a CCD or CMOS imaging structure.

    摘要翻译: 公开了一种用于制造背照式半导体成像装置和所得到的成像装置的方法,其包括提供具有前表面和后表面的基板的步骤; 生长基本上覆盖在衬底的前表面上的外延层; 在所述外延层中基本上形成至少一个阻挡层; 制造覆盖并延伸到所述外延层中的至少一个成像结构,所述成像结构至少一个电荷转移区域,所述至少一个阻挡层基本上位于所述至少一个电荷转移区域的下方,其中入射在所述基底的背面上的光 产生通过至少一个阻挡层从所述至少一个电荷转移区域转移的电荷载流子。 使用外延横向过度生长技术生长外延层的至少一部分。 阻挡层可以是基本上在外延层内形成的高能量注入,由在所有侧面被氧化物包围的光学不透明材料制成的光屏蔽,或两者的组合。 该成像结构可以是CCD或CMOS成像结构。

    Multiple high-resolution serum proteomic features for ovarian cancer detection
    4.
    发明申请
    Multiple high-resolution serum proteomic features for ovarian cancer detection 审中-公开
    用于卵巢癌检测的多种高分辨率血清蛋白质组学特征

    公开(公告)号:US20060064253A1

    公开(公告)日:2006-03-23

    申请号:US11093018

    申请日:2005-03-30

    申请人: Ben Hitt Peter Levine

    发明人: Ben Hitt Peter Levine

    IPC分类号: G06F19/00

    CPC分类号: G16B20/00 G16B40/00

    摘要: A well-controlled serum study set (n=248) from women being followed and evaluated for the presence of ovarian cancer was used to extend serum proteomic pattern analysis to a higher resolution mass spectrometer instrument platform to explore the existence of multiple distinct highly accurate diagnostic sets of features present in the same mass spectrum. Multiple highly accurate diagnostic proteomic feature sets exist within human sera mass spectra. Using high-resolution mass spectral data, at least 56 different patterns were discovered that achieve greater than 85% sensitivity and specificity in testing and validation. Four of those feature sets exhibited 100% sensitivity and specificity in blinded validation. The sensitivity and specificity of diagnostic models generated from high-resolution mass spectral data were superior (P

    摘要翻译: 使用来自妇女的良好控制的血清研究组(n = 248)并评估卵巢癌的存在,将血清蛋白质组学模式分析扩展到更高分辨率的质谱仪仪器平台,以探索存在多种不同的高精度诊断 在同一质谱中存在的特征集合。 人血清质谱中存在多个高度准确的诊断蛋白质组特征集。 使用高分辨率质谱数据,发现了至少56种不同的模式,其在测试和验证中实现了大于85%的灵敏度和特异性。 其中四个特征集在盲法验证中表现出100%的灵敏度和特异性。 从高分辨率质谱数据生成的诊断模型的灵敏度和特异性优于使用相同输入样本的低分辨率质谱数据产生的诊断模型的灵敏度和特异性(P <0.00001)。

    Method of fabricating back-illuminated imaging sensors using a bump bonding technique
    6.
    发明授权
    Method of fabricating back-illuminated imaging sensors using a bump bonding technique 有权
    使用凸块接合技术制造背照式成像传感器的方法

    公开(公告)号:US07932575B2

    公开(公告)日:2011-04-26

    申请号:US12431150

    申请日:2009-04-28

    IPC分类号: H01L21/00

    摘要: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer and the at least one imaging component; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads.

    摘要翻译: 公开了一种用于在绝缘体上半导体衬底上制造背照式半导体成像器件的方法,以及所得成像器件。 用于制造成像装置的方法包括以下步骤:提供包括绝缘体层的基板和基本上覆盖绝缘体层的外延层; 制造至少部分地覆盖并延伸到所述外延层中的至少一个成像部件; 形成基本上覆盖所述外延层的多个接合焊盘; 制造基本上覆盖所述外延层和所述至少一个成像部件的电介质层; 提供处理晶片; 在所述手柄晶片中形成多个导电沟槽; 在所述处理晶片的位于所述导电沟槽下面的第一表面上形成多个导电凸块; 以及将所述多个导电凸块接合到所述多个接合焊盘。

    Method and apparatus for reducing smear in back-illuminated imaging sensors
    7.
    发明授权
    Method and apparatus for reducing smear in back-illuminated imaging sensors 有权
    用于减少背照式成像传感器中的涂片的方法和装置

    公开(公告)号:US07777229B2

    公开(公告)日:2010-08-17

    申请号:US11844775

    申请日:2007-08-24

    IPC分类号: H01L27/14

    摘要: A method for fabricating a back-illuminated semiconductor imaging device and resulting imaging device is disclosed, which includes the steps providing a substrate having a front surface and a back surface; growing an epitaxial layer substantially overlying the front surface of the substrate; forming at least one barrier layer substantially within the epitaxial layer; fabricating at least one imaging structure overlying and extending into the epitaxial layer, the imaging structure at least one charge transfer region, the at least one barrier layer substantially underlying the at least one charge transfer region, wherein light incident on the back surface of the substrate generates charge carriers which are diverted away from the at least one charge transfer region by the at least one barrier layer. At least a portion of the epitaxial layer is grown using an epitaxial lateral overgrowth technique. The barrier layer can be a high energy implant formed substantially within the epitaxial layer, an optical shield made of an optically opaque material surrounded by oxide on all sides, or a combination of both. The imaging structure can be a CCD or CMOS imaging structure.

    摘要翻译: 公开了一种用于制造背照式半导体成像装置和所得到的成像装置的方法,其包括提供具有前表面和后表面的基板的步骤; 生长基本上覆盖在衬底的前表面上的外延层; 在所述外延层中基本上形成至少一个阻挡层; 制造覆盖并延伸到所述外延层中的至少一个成像结构,所述成像结构至少一个电荷转移区域,所述至少一个阻挡层基本上位于所述至少一个电荷转移区域的下方,其中入射在所述基底的背面上的光 产生通过至少一个阻挡层从所述至少一个电荷转移区域转移的电荷载流子。 使用外延横向过度生长技术生长外延层的至少一部分。 阻挡层可以是基本上在外延层内形成的高能量注入,由在所有侧面被氧化物包围的光学不透明材料制成的光屏蔽,或两者的组合。 该成像结构可以是CCD或CMOS成像结构。

    Method of fabricating back-illuminated imaging sensors
    8.
    发明授权
    Method of fabricating back-illuminated imaging sensors 有权
    制造背照式成像传感器的方法

    公开(公告)号:US07622342B2

    公开(公告)日:2009-11-24

    申请号:US12020640

    申请日:2008-01-28

    IPC分类号: H01L21/8238

    摘要: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. A substrate which includes an insulator layer and an epitaxial layer substantially overlying the insulator layer is provided. At least one bond pad region is formed extending into the epitaxial layer to a surface of the insulator layer. At least one bond pad is fabricated at least partially overlying the at least one bond pad region. At least one imaging component is fabricated at least partially overlying and extending into the epitaxial layer. A passivation layer is fabricated substantially overlying the epitaxial layer, the at least one bond pad, and the at least one imaging component. A handle wafer is bonded to the passivation layer. The at least a portion of the insulator layer and at least a portion of the bond pad region is etched to expose at least a portion of the at least one bond pad.

    摘要翻译: 公开了一种用于在绝缘体上半导体衬底上制造背照式半导体成像器件的方法,以及所得成像器件。 提供了包括绝缘体层和基本上覆盖绝缘体层的外延层的衬底。 形成延伸到外延层中至少一个接合焊盘区域到绝缘体层的表面。 制造至少部分地覆盖至少一个接合焊盘区域的至少一个接合焊盘。 制造至少部分地覆盖并延伸到外延层中的至少一个成像部件。 制造基本上覆盖外延层,至少一个接合焊盘和至少一个成像部件的钝化层。 处理晶片结合到钝化层。 绝缘体层的至少一部分和接合焊盘区域的至少一部分被蚀刻以暴露至少一个接合焊盘的至少一部分。

    Method of Fabricating Back-Illuminated Imaging Sensors Using a Bump Bonding Technique
    9.
    发明申请
    Method of Fabricating Back-Illuminated Imaging Sensors Using a Bump Bonding Technique 有权
    使用凸块接合技术制造背照射成像传感器的方法

    公开(公告)号:US20080237762A1

    公开(公告)日:2008-10-02

    申请号:US11779414

    申请日:2007-07-18

    IPC分类号: H01L31/0232 H01L31/18

    摘要: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer and the at least one imaging component; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads.

    摘要翻译: 公开了一种用于在绝缘体上半导体衬底上制造背照式半导体成像器件的方法,以及所得成像器件。 用于制造成像装置的方法包括以下步骤:提供包括绝缘体层的基板和基本上覆盖绝缘体层的外延层; 制造至少部分地覆盖并延伸到所述外延层中的至少一个成像部件; 形成基本上覆盖所述外延层的多个接合焊盘; 制造基本上覆盖所述外延层和所述至少一个成像部件的电介质层; 提供处理晶片; 在所述手柄晶片中形成多个导电沟槽; 在所述处理晶片的位于所述导电沟槽下面的第一表面上形成多个导电凸块; 以及将所述多个导电凸块接合到所述多个接合焊盘。

    Dark Current Reduction in Back-Illuminated Imaging Sensors and Method of Fabricating Same
    10.
    发明申请
    Dark Current Reduction in Back-Illuminated Imaging Sensors and Method of Fabricating Same 有权
    背照光成像传感器的暗电流降低及其制造方法

    公开(公告)号:US20070235829A1

    公开(公告)日:2007-10-11

    申请号:US11752601

    申请日:2007-05-23

    IPC分类号: H01L31/0232 H01L31/18

    摘要: A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more imaging components in the epitaxial layer in proximity to a face of the epitaxial layer, the face being opposite the interface of the semiconductor substrate and the insulator layer, the imaging components comprising junctions within the epitaxial layer; wherein the semiconductor substrate and the epitaxial layer exhibit a net doping concentration having a maximum value at a predetermined distance from the interface of the insulating layer and the semiconductor substrate and which decreases monotonically on both sides of the profile from the maximum value within a portion of the semiconductor substrate and the epitaxial layer. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device.

    摘要翻译: 公开了一种用于在绝缘体上半导体衬底上制造背照式半导体成像器件的方法,以及所得成像器件。 该装置包括绝缘体层; 半导体衬底,与绝缘体层具有界面; 通过外延生长在半导体衬底上生长的外延层; 以及在所述外延层中靠近所述外延层的表面的一个或多个成像组件,所述表面与所述半导体衬底和所述绝缘体层的界面相对,所述成像组件包括所述外延层内的结; 其中所述半导体衬底和所述外延层表现出净绝缘浓度,所述净掺杂浓度在距所述绝缘层和所述半导体衬底的界面预定距离处具有最大值,并且所述净掺杂浓度在所述剖面的两侧上从所述最大值的单一部分 半导体衬底和外延层。 与绝缘层的界面和掺杂分布的峰值之间的掺杂分布用作“死区”,以防止暗电流载流子穿透到器件的前侧。