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    Method of manufacturing a display substrate and method of manufacturing a display apparatus using the same
    1.
    发明授权
    Method of manufacturing a display substrate and method of manufacturing a display apparatus using the same 失效
    显示基板的制造方法及使用其的显示装置的制造方法

    公开(公告)号：US08557620B2

    公开(公告)日：2013-10-15

    申请号：US12421555

    申请日：2009-04-09

    Applicant: Pil-Soon Hong ,  Jung-In Park ,  Hi-Kuk Lee

    Inventor： Pil-Soon Hong ,  Jung-In Park ,  Hi-Kuk Lee

    IPC: H01L21/00

    CPC classification number: H01L27/1288 ,  H01L27/3248 ,  H01L2227/323

    Abstract: Provided is a method of manufacturing a display substrate. In the method, a gate line, a data line crossing the gate line, and a switching device are formed on a base substrate. A passivation layer, a first resist layer and a second resist layer are formed on the base substrate. The first resist layer and the second resist layer are patterned to form a resist pattern and an etch-stop pattern, the etch-stop pattern having a sidewall protruding from a sidewall of the resist pattern. A portion of the passivation layer is removed to form a contact hole on a drain electrode of the switching device. A pixel electrode electrically connected to the switching device through the contact hole is formed. Thus, an undercut between an etch-stop pattern and a resist pattern may be more easily formed without over-etching a passivation layer.

    Abstract translation: 提供一种制造显示基板的方法。 在该方法中，在基底基板上形成栅极线，与栅极线交叉的数据线以及开关元件。 在基底基板上形成钝化层，第一抗蚀剂层和第二抗蚀剂层。 图案化第一抗蚀剂层和第二抗蚀剂层以形成抗蚀剂图案和蚀刻停止图案，该蚀刻停止图案具有从抗蚀剂图案的侧壁突出的侧壁。 去除钝化层的一部分以在开关器件的漏电极上形成接触孔。 形成通过接触孔与开关装置电连接的像素电极。 因此，可以更容易地形成蚀刻停止图案和抗蚀剂图案之间的底切，而不会过度蚀刻钝化层。

    METHOD OF MANUFACTURING IMPRINT SUBSTRATE AND IMPRINTING METHOD
    3.
    发明申请
    METHOD OF MANUFACTURING IMPRINT SUBSTRATE AND IMPRINTING METHOD 有权
    制造印刷基板和印刷方法的方法

    公开(公告)号：US20090286379A1

    公开(公告)日：2009-11-19

    申请号：US12260974

    申请日：2008-10-29

    Applicant: Pil-Soon HONG

    Inventor： Pil-Soon HONG

    IPC: H01L21/762 ,  B32B38/10 ,  G03F7/20

    CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

    Abstract: In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed.

    Abstract translation: 在制造压印基板的方法中，在模具基板的顶表面上形成凹陷的凹形图案。 在凹形图案和模制基板的顶表面上形成遮光层。 在将粘合剂基材粘合到模具基材上使得粘合剂基材面向模具基材之后，将粘合剂基材与模塑基材分离，从而将顶表面上的遮光层从模制基材上除去。 形成仅在凹形图案上具有遮光层的压印基板。

    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF 失效
    薄膜晶体管阵列及其制造方法

    公开(公告)号：US20130087800A1

    公开(公告)日：2013-04-11

    申请号：US13424278

    申请日：2012-03-19

    Applicant: Pil Soon HONG ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

    Inventor： Pil Soon HONG ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

    IPC: H01L27/15 ,  H01L33/08

    CPC classification number: H01L27/124 ,  H01L29/41733

    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

    Abstract translation: 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

    FLATTENING METHOD OF A SUBSTRATE
    6.
    发明申请
    FLATTENING METHOD OF A SUBSTRATE 有权
    基板的平铺方法

    公开(公告)号：US20120149158A1

    公开(公告)日：2012-06-14

    申请号：US13074296

    申请日：2011-03-29

    Applicant: Pil Soon HONG ,  Gwui-Hyun PARK ,  Sang Gab KIM

    Inventor： Pil Soon HONG ,  Gwui-Hyun PARK ,  Sang Gab KIM

    IPC: H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/4908 ,  H01L27/1248 ,  H01L27/1288

    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.

    Abstract translation: 一种使基板平坦化的方法包括在基板的上表面上形成金属层，形成覆盖基板和金属层的光致抗蚀剂层，通过与上表面相对的基板的下表面向光致抗蚀剂层照射光 通过显影光致抗蚀剂层来暴露金属层，通过蚀刻金属层暴露衬底的上表面，蚀刻暴露的衬底的上表面，以及去除光致抗蚀剂层。

    Method of manufacturing imprint substrate and imprinting method
    7.
    发明授权
    Method of manufacturing imprint substrate and imprinting method 有权
    压印基板和压印方法的制作方法

    公开(公告)号：US07781345B2

    公开(公告)日：2010-08-24

    申请号：US12260974

    申请日：2008-10-29

    Applicant: Pil-Soon Hong

    Inventor： Pil-Soon Hong

    IPC: H01L21/312

    CPC classification number: G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

    Abstract: In a method of manufacturing an imprint substrate, a concave pattern, which is recessed, is formed on a top surface of the mold substrate. A light blocking layer is formed on the concave pattern and the top surface of the mold substrate. After bonding an adhesive substrate to the mold substrate such that the adhesive substrate faces the mold substrate, the adhesive substrate is separated from the mold substrate, so that the light blocking layer on the top surface is removed from the mold substrate. An imprint substrate having the light blocking layer only on the concave pattern is formed.

    Abstract translation: 在制造压印基板的方法中，在模具基板的顶表面上形成凹陷的凹形图案。 在凹形图案和模制基板的顶表面上形成遮光层。 在将粘合剂基材粘合到模具基材上使得粘合剂基材面向模具基材之后，将粘合剂基材与模塑基材分离，从而将顶表面上的遮光层从模制基材上除去。 形成仅在凹形图案上具有遮光层的压印基板。

    Thin film transistor array panel
    8.
    发明授权
    Thin film transistor array panel 失效
    薄膜晶体管阵列面板

    公开(公告)号：US08653530B2

    公开(公告)日：2014-02-18

    申请号：US13424278

    申请日：2012-03-19

    Applicant: Pil Soon Hong ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

    Inventor： Pil Soon Hong ,  Gwui-Hyun Park ,  Jin-Su Byun ,  Sang Gab Kim

    IPC: H01L29/00

    CPC classification number: H01L27/124 ,  H01L29/41733

    Abstract: The present invention relates to a thin film transistor array panel and a manufacturing method thereof that prevent disconnection of wiring due to misalignment of a mask, and simplify a process and reduce cost by reducing the number of masks. The thin film transistor array panel according to the disclosure includes a source electrode enclosing an outer part of the first contact hole and formed on the second insulating layer; a drain electrode enclosing an outer part of the second contact hole and formed on the second insulating layer; a first connection electrode connecting the source region of the semiconductor layer and the source electrode through the first contact hole; and a second connection electrode connecting the drain region of the semiconductor layer and the drain electrode through the second contact hole.

    Abstract translation: 薄膜晶体管阵列面板及其制造方法技术领域本发明涉及一种薄膜晶体管阵列面板及其制造方法，其能够防止由于掩模的未对准而使布线断开，并且通过减少掩模数来简化处理并降低成本。 根据本发明的薄膜晶体管阵列面板包括：源电极，其包围第一接触孔的外部部分并形成在第二绝缘层上; 漏电极，其包围所述第二接触孔的外部部分并形成在所述第二绝缘层上; 第一连接电极，通过第一接触孔连接半导体层的源极区域和源极电极; 以及通过第二接触孔连接半导体层的漏极区域和漏极电极的第二连接电极。

    Flattening method of a substrate
    9.
    发明授权
    Flattening method of a substrate 有权
    基板的平整方法

    公开(公告)号：US08450160B2

    公开(公告)日：2013-05-28

    申请号：US13074296

    申请日：2011-03-29

    Applicant: Pil Soon Hong ,  Gwui-Hyun Park ,  Sang Gab Kim

    Inventor： Pil Soon Hong ,  Gwui-Hyun Park ,  Sang Gab Kim

    IPC: H01L21/84

    CPC classification number: H01L29/4908 ,  H01L27/1248 ,  H01L27/1288

    Abstract: A method of flattening a substrate includes forming a metal layer on an upper surface of a substrate, forming a photoresist layer covering the substrate and the metal layer, radiating light to the photoresist layer, through a lower surface of the substrate opposite to the upper surface, exposing the metal layer by developing the photoresist layer, exposing the upper surface of the substrate by etching the metal layer, etching the exposed upper surface of the substrate, and removing the photoresist layer.

    Abstract translation: 一种使基板平坦化的方法包括在基板的上表面上形成金属层，形成覆盖基板和金属层的光致抗蚀剂层，通过与上表面相对的基板的下表面向光致抗蚀剂层照射光 通过显影光致抗蚀剂层来暴露金属层，通过蚀刻金属层暴露衬底的上表面，蚀刻暴露的衬底的上表面，以及去除光致抗蚀剂层。

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