公开(公告)号：US07927919B1

公开(公告)日：2011-04-19

申请号：US12630623

申请日：2009-12-03

申请人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

发明人： Wen-Jeng Fan ,  Li-Chih Fang ,  Ronald Takao Iwata

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.

摘要翻译： 揭示了没有插入器的半导体封装方法。 母芯片是由半导体层和有机层组成的两层结构，其中再分布层被嵌入到有机层中，多个第一端子和多个第二端子设置在再分配层上并从有机层暴露出来 层。 母芯片倒装芯片安装在基板上。 子芯片的有源面与有机层接触，子芯片的接合焊盘与第一端子接合。 此外，多个电连接部件将第二端子电连接到基板。 在多芯片堆叠封装中，可以以更薄的整体封装厚度以及受控的封装翘曲消除中介层。

公开(公告)号：US20080087999A1

公开(公告)日：2008-04-17

申请号：US11581085

申请日：2006-10-16

申请人： Ronald Takao Iwata

发明人： Ronald Takao Iwata

IPC分类号： H01L23/00

CPC分类号： H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A micro BGA package comprises a first chip, a second chip, a single-layer PCB, a plurality of bonding wires, an encapsulant and a plurality of solder balls. The second chip is smaller than the first chip in size and stacked on the active surface of the first surface by facing the same direction with the first chip without covering the bonding pads of the first chip. The single-layer PCB is disposed on the second chip and smaller than the second chip in size. The single-layer PCB has a single-layer wiring pattern including a plurality of wire-connecting pads and a plurality of ball pads. By wire-bonding method, the first and second chips are electrically connected to the wire-connecting pads. The encapsulant is formed around the first chip, the second chip and the single-layer PCB to seal the bonding wires but exposes the rear surface of the first chip and the solder balls. The solder balls are disposed on the ball pads. Accordingly, the micro BGA package may reduce package size of multi-chip stack and improve thermal dissipation without increasing package thickness.

摘要翻译： 微BGA封装包括第一芯片，第二芯片，单层PCB，多个接合线，密封剂和多个焊球。 第二芯片尺寸小于第一芯片，并且通过面向与第一芯片相同的方向堆叠在第一表面的有源表面上，而不覆盖第一芯片的焊盘。 单层PCB设置在第二芯片上并且小于第二芯片的尺寸。 单层PCB具有包括多个线连接焊盘和多个焊盘的单层布线图案。 通过引线接合方法，第一和第二芯片电连接到导线连接焊盘。 密封剂形成在第一芯片，第二芯片和单层PCB周围，以密封接合线，但暴露第一芯片和焊球的后表面。 焊球设置在球垫上。 因此，微BGA封装可以减小多芯片堆叠的封装尺寸，并且在不增加封装厚度的情况下改善热耗散。

公开(公告)号：US20100167534A1

公开(公告)日：2010-07-01

申请号：US12722251

申请日：2010-03-11

申请人： Ronald Takao IWATA

发明人： Ronald Takao IWATA

IPC分类号： H01L21/768

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/78301 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/451 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

摘要： A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active surface to the back surface, in which an insulation layer is disposed. The flexible metal wire has a first terminal and a second terminal where the first terminal is bonded to a redistributed pad of the redistributed trace layer and the second terminal passes through the through hole and protrudes from the back surface of the chip. Therefore, the flexible metal wire passing through the chip has two protruded integral terminals to achieve high stress resistance TSV with lower costs for good electrical connections of vertical stacking chips.

摘要翻译： 揭示了具有TSV的半导体器件及其制造方法。 半导体器件主要包括芯片和内部的柔性金属线。 在芯片的有源表面上形成再分布的迹线层和钝化层。 通孔从活性表面穿透芯片到背面，其中设置绝缘层。 柔性金属线具有第一端子和第二端子，其中第一端子接合到再分布的迹线层的重新分布的焊盘，并且第二端子穿过通孔并从芯片的后表面突出。 因此，穿过芯片的柔性金属线具有两个突出的集成端子，以实现高应力阻力TSV，具有较低的成本，用于垂直堆叠芯片的良好电连接。

公开(公告)号：US20090127667A1

公开(公告)日：2009-05-21

申请号：US11984785

申请日：2007-11-21

申请人： Ronald Takao Iwata

发明人： Ronald Takao Iwata

IPC分类号： H01L23/48 ,  H01L21/304

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/78 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/136 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/78301 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/451 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

摘要： A semiconductor device with TSV and its fabrication method are revealed. The semiconductor device primarily comprises a chip and a flexible metal wire inside. A redistributed trace layer and a passivation layer are formed on the active surface of the chip. A through hole penetrates the chip from the active surface to the back surface, in which an insulation layer is disposed. The flexible metal wire has a first terminal and a second terminal where the first terminal is bonded to a redistributed pad of the redistributed trace layer and the second terminal passes through the through hole and protrudes from the back surface of the chip. Therefore, the flexible metal wire passing through the chip has two protruded integral terminals to achieve high stress resistance TSV with lower costs for good electrical connections of vertical stacking chips.

摘要翻译： 揭示了具有TSV的半导体器件及其制造方法。 半导体器件主要包括芯片和内部的柔性金属线。 在芯片的有源表面上形成再分布的迹线层和钝化层。 通孔从活性表面穿透芯片到背面，其中设置绝缘层。 柔性金属线具有第一端子和第二端子，其中第一端子接合到再分布的迹线层的重新分布的焊盘，并且第二端子穿过通孔并从芯片的后表面突出。 因此，穿过芯片的柔性金属线具有两个突出的集成端子，以实现高应力阻力TSV，具有较低的成本，用于垂直堆叠芯片的良好电连接。

公开(公告)号：US20080088005A1

公开(公告)日：2008-04-17

申请号：US11581084

申请日：2006-10-16

申请人： Ronald Takao Iwata

发明人： Ronald Takao Iwata

IPC分类号： H01L23/48

CPC分类号： H01L23/3128 ,  H01L23/13 ,  H01L24/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A SIP package with a small dimension integrates one or more small size chips. The small size chips are disposed on a back side of a carrying chip and are encapsulated by an encapsulant. The SIP package further includes a substrate having a slot, an encapsulant and a plurality of bonding wires. The carrying chip is disposed on the substrate and the bonding pads of the carrying chip are aligned within the slot. A back side pattern is formed on the back side of the carrying chip. The chip-attached area of the small size chips is smaller than half of that of the back side of the carrying chip. Besides, the back side pattern is connected with a plurality of transfer fingers or a plurality of PTHs at the periphery of the back side for electrically connecting the small size chips to the substrate. Accordingly, the bonding wires used for connecting the small size chips can be shortened and regulated to achieve miniaturization of SIP package without increasing package size and thickness.

摘要翻译： 具有小尺寸的SIP封装集成了一个或多个小尺寸芯片。 小尺寸芯片设置在承载芯片的背面并且由密封剂封装。 SIP封装还包括具有槽的衬底，密封剂和多个接合线。 承载芯片设置在基板上，并且承载芯片的接合焊盘在槽内对准。 背面图案形成在承载芯片的背面。 小尺寸芯片的芯片附着面积小于载体芯片背面的一半。 此外，背面图案与背侧的周边处的多个传送指状物或多个PTH连接，用于将小尺寸的芯片电连接到基板。 因此，可以缩短和调节用于连接小尺寸芯片的接合线，以实现SIP封装的小型化，而不增加封装尺寸和厚度。