公开(公告)号：US20070188256A1

公开(公告)日：2007-08-16

申请号：US11351987

申请日：2006-02-10

申请人： Sanjeev Maheshwari

发明人： Sanjeev Maheshwari

IPC分类号： H03L7/099

CPC分类号： H03B5/364 ,  H03B2200/0062

摘要： An oscillator amplifier circuit is provided. The amplifier circuit can be used with a resonator to amplify and form a resonating oscillator. The amplifier circuit comprises an active circuit which includes an inverter and a current-controlled biasing circuit. One transistor of the inverter receives a voltage produced from the biasing circuit in order to place a gate terminal of that transistor at approximately a threshold voltage. The other transistor can be biased using a passive circuit element, such as a resistor. Therefore, both transistors are biased independent of each other within the optimal gain region. Large shunt capacitors are not required and the total current consumption is controlled through a variable resistor coupled to the source terminal of either the first transistor, second transistor, or possibly both transistors of the inverter to adjust the amplitude of the oscillating output.

摘要翻译： 提供振荡放大器电路。 放大器电路可以与谐振器一起使用以放大并形成谐振振荡器。 放大器电路包括有源电路，其包括反相器和电流控制偏置电路。 逆变器的一个晶体管接收从偏置电路产生的电压，以将该晶体管的栅极端子置于大约阈值电压。 另一个晶体管可以使用诸如电阻器的无源电路元件来偏置。 因此，两个晶体管在最佳增益区域内彼此独立地偏置。 不需要大分流电容器，并且通过耦合到第一晶体管，第二晶体管的源极端子或可能的两个晶体管的可变电阻器来控制总电流消耗，以调整振荡输出的幅度。

公开(公告)号：US20120056653A1

公开(公告)日：2012-03-08

申请号：US12875337

申请日：2010-09-03

申请人： Sanjeev MAHESHWARI ,  Emerson FANG

发明人： Sanjeev MAHESHWARI ,  Emerson FANG

IPC分类号： H03L7/08

CPC分类号： H03L7/091 ,  H03L7/0998 ,  H03L2207/50

摘要： Apparatus, systems and methods are provided for digital phase-locked loops. A digital phase-locked loop comprises an oscillator module configured to generate an output signal and a phase detection module coupled to the oscillator module. The phase detection module is configured to signal the oscillator module to adjust a frequency of the output signal by a first amount when a phase difference between a reference signal and the output signal is less than a threshold amount, and signal the oscillator module to adjust the frequency by a greater amount when the phase difference is greater than the threshold amount.

摘要翻译： 为数字锁相环提供了装置，系统和方法。 数字锁相环包括被配置为产生输出信号的振荡器模块和耦合到振荡器模块的相位检测模块。 相位检测模块被配置为当参考信号和输出信号之间的相位差小于阈值时，使振荡器模块发信号将输出信号的频率调整第一量，并且向振荡器模块发信号以调整 当相位差大于阈值时，频率增加更多的量。

公开(公告)号：US07817761B2

公开(公告)日：2010-10-19

申请号：US11756674

申请日：2007-06-01

申请人： Meei-Ling Chiang ,  Dwight K. Elvey ,  Sanjeev Maheshwari ,  Emerson S. Fang

发明人： Meei-Ling Chiang ,  Dwight K. Elvey ,  Sanjeev Maheshwari ,  Emerson S. Fang

IPC分类号： H04L7/00 ,  H03L7/06

CPC分类号： G01R31/3016 ,  G01R31/31725 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/091

摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

摘要翻译： 集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。 集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。 第一时钟信号是至少一个延迟时钟信号的第一版本。 所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。 集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

公开(公告)号：US08269533B2

公开(公告)日：2012-09-18

申请号：US12875337

申请日：2010-09-03

申请人： Sanjeev Maheshwari ,  Emerson Fang

发明人： Sanjeev Maheshwari ,  Emerson Fang

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/0998 ,  H03L2207/50

摘要： Apparatus, systems and methods are provided for digital phase-locked loops. A digital phase-locked loop comprises an oscillator module configured to generate an output signal and a phase detection module coupled to the oscillator module. The phase detection module is configured to signal the oscillator module to adjust a frequency of the output signal by a first amount when a phase difference between a reference signal and the output signal is less than a threshold amount, and signal the oscillator module to adjust the frequency by a greater amount when the phase difference is greater than the threshold amount.

摘要翻译： 为数字锁相环提供了装置，系统和方法。 数字锁相环包括被配置为产生输出信号的振荡器模块和耦合到振荡器模块的相位检测模块。 相位检测模块被配置为当参考信号和输出信号之间的相位差小于阈值时，使振荡器模块发信号将输出信号的频率调整第一量，并且向振荡器模块发信号以调整 当相位差大于阈值时，频率增加更多的量。

公开(公告)号：US20080273528A1

公开(公告)日：2008-11-06

申请号：US11742860

申请日：2007-05-01

申请人： Sanjeev Maheshwari ,  Meei-Ling Chiang ,  Emerson S. Fang

发明人： Sanjeev Maheshwari ,  Meei-Ling Chiang ,  Emerson S. Fang

IPC分类号： H04L12/50

CPC分类号： H04L7/0337 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025

摘要： A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.

摘要翻译： 相位信号选择电路包括耦合到三态反相器电路的支撑路径。 支持路径减少了滞后对信号传输的影响。 一种装置包括响应于至少一个输入信号中的相应一个的至少一个输入节点。 该装置包括耦合到至少一个输入节点中的相应一个并耦合到输出节点的至少一个电路。 所述至少一个电路中的各个电路被配置为响应于相应选择信号的第一状态而将相应输入信号的形式提供给输出节点。 该装置包括耦合到至少一个电路中的相应一个电路的至少一个第二电路。 至少一个第二电路被配置为响应于相应选择信号的第二状态来切换至少一个电路的节点。

公开(公告)号：US20080272814A1

公开(公告)日：2008-11-06

申请号：US11742845

申请日：2007-05-01

申请人： Meei-Ling Chiang ,  Sanjeev Maheshwari ,  Emerson S. Fang

发明人： Meei-Ling Chiang ,  Sanjeev Maheshwari ,  Emerson S. Fang

IPC分类号： H03K3/017

CPC分类号： H03K3/017

摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.

摘要翻译： 接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。 占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

公开(公告)号：US20060114020A1

公开(公告)日：2006-06-01

申请号：US11234429

申请日：2005-09-23

申请人： Babak Taheri ,  Sanjeev Maheshwari

发明人： Babak Taheri ,  Sanjeev Maheshwari

IPC分类号： H03K19/173

CPC分类号： G11C17/146 ,  G11C14/00 ,  G11C17/16

摘要： A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

摘要翻译： 一次性可编程（OTP）锁存电路可以包括能够以非易失性方式存储逻辑值的单个OTP设备，或者在需要冗余的情况下仅包括两个OTP设备。 基于根据一个OTP设备绘制的电流与不使用OTP设备的参考电流进行比较，锁存部分可以锁定数据值。 OTP设备可以包括栅极氧化物反熔丝（GOAF）器件。

公开(公告)号：US20050207223A1

公开(公告)日：2005-09-22

申请号：US10803011

申请日：2004-03-17

申请人： Babak Taheri ,  Sanjeev Maheshwari ,  Fredrick Jenne

发明人： Babak Taheri ,  Sanjeev Maheshwari ,  Fredrick Jenne

IPC分类号： G11C7/20 ,  G11C14/00

CPC分类号： G11C7/20

摘要： A latching circuit is provided that includes a latch, a storage element, and a selection circuit coupled between the latch and the storage element. The latch can receive true and complementary voltage values from, for example, a data bus and, if called upon, forward the latched value to the non-volatile storage element via the selection circuit. Control signals sent to the selection circuit allow the latched data to be written to or read from the storage element. Once programmed, the voltage values will remain in the latching circuit even after power is removed. If the latched data is not sent to the non-volatile storage element, the latching circuit essentially functions as a volatile latch, and the data will be lost if power is removed. The switching circuit thereby operates as a dual-purpose volatile and non-volatile latching circuit that can be embodied as an array of latching circuits that temporarily and/or permanently store true and complementary data signals.

摘要翻译： 提供了一种闭锁电路，其包括闩锁，存储元件以及耦合在闩锁和存储元件之间的选择电路。 锁存器可以从例如数据总线接收真实和互补的电压值，并且如果被调用，经由选择电路将锁存值转发到非易失性存储元件。 发送到选择电路的控制信号允许将锁存的数据写入存储元件或从存储元件读取。 一旦被编程，即使在掉电后，电压值也将保持在锁存电路中。 如果锁存的数据未被发送到非易失性存储元件，则锁存电路基本上用作易失性锁存器，并且如果去掉电源，则数据将丢失。 因此，切换电路作为双功能易失性和非易失性的锁存电路来操作，其可被实现为临时和/或永久地存储真实和互补数据信号的锁存电路阵列。

公开(公告)号：US08451064B2

公开(公告)日：2013-05-28

申请号：US12900163

申请日：2010-10-07

申请人： Sanjeev Maheshwari ,  Emerson Fang ,  Sanjeev Aggarwal

发明人： Sanjeev Maheshwari ,  Emerson Fang ,  Sanjeev Aggarwal

IPC分类号： H03L7/18

CPC分类号： H03L7/0998

摘要： Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.

摘要翻译： 提供了具有可调增益的振荡器的装置和方法。 示例性振荡器模块包括用于第一电压的第一节点，用于控制信号的控制节点和耦合到第一节点和控制节点的振荡器电路。 振荡器电路基于第一电压产生具有第一振荡频率的输出信号，并且响应于控制信号被断言，振荡器电路基于第一电压产生具有第二振荡频率的输出信号。 第二振荡频率大于第一振荡频率。

公开(公告)号：US20120086482A1

公开(公告)日：2012-04-12

申请号：US12900163

申请日：2010-10-07

申请人： Sanjeev MAHESHWARI ,  Emerson FANG ,  Sanjeev AGGARWAL

发明人： Sanjeev MAHESHWARI ,  Emerson FANG ,  Sanjeev AGGARWAL

IPC分类号： H03L7/08 ,  H03L5/00

CPC分类号： H03L7/0998

摘要： Apparatus and methods are provided for oscillators having adjustable gain. An exemplary oscillator module comprises a first node for a first voltage, a control node for a control signal, and oscillator circuitry coupled to the first node and the control node. The oscillator circuitry generates an output signal with a first oscillation frequency based on the first voltage, and in response to the control signal being asserted, the oscillator circuitry generates the output signal with a second oscillation frequency based on the first voltage. The second oscillation frequency is greater than the first oscillation frequency.

摘要翻译： 提供了具有可调增益的振荡器的装置和方法。 示例性振荡器模块包括用于第一电压的第一节点，用于控制信号的控制节点和耦合到第一节点和控制节点的振荡器电路。 振荡器电路基于第一电压产生具有第一振荡频率的输出信号，并且响应于控制信号被断言，振荡器电路基于第一电压产生具有第二振荡频率的输出信号。 第二振荡频率大于第一振荡频率。