公开(公告)号：US08519524B1

公开(公告)日：2013-08-27

申请号：US13586890

申请日：2012-08-16

申请人： Sheng-Tsai Wu ,  John H. Lau ,  Heng-Chieh Chien ,  Ra-Min Tain ,  Ming-Ji Dai ,  Yu-Lin Chao

发明人： Sheng-Tsai Wu ,  John H. Lau ,  Heng-Chieh Chien ,  Ra-Min Tain ,  Ming-Ji Dai ,  Yu-Lin Chao

IPC分类号： H01L23/02

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17104 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/01074 ,  H01L2224/03 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/05552

摘要： A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.

摘要翻译： 提供了包括载体，第一再分布层，第二再分配层，至少一个第一芯片，至少一个第二芯片和至少一个导体的芯片堆叠结构。 载体具有彼此相对的第一表面和第二表面。 载体具有至少一个通孔。 第一和第二再分布层分别设置在载体的第一和第二表面上。 第一和第二芯片设置在载体的第一和第二表面上，并分别与第一和第二再分配层电连接。 导体设置在第一和第二芯片之一上。 导体设置在通孔中。 第一和第二芯片由导体电连接。 在导体和围绕通孔的载体的内壁之间形成间隙。