公开(公告)号：US20070108520A1

公开(公告)日：2007-05-17

申请号：US11399427

申请日：2006-04-07

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US07829408B2

公开(公告)日：2010-11-09

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US07525153B2

公开(公告)日：2009-04-28

申请号：US11399427

申请日：2006-04-07

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US20090209075A1

公开(公告)日：2009-08-20

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US20060044718A1

公开(公告)日：2006-03-02

申请号：US10933181

申请日：2004-09-02

申请人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

摘要翻译： 用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。 有源P环围绕具有与半导体衬底相同导电类型的导电区域的晶体管的源极和漏极。 耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。 偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

公开(公告)号：US06947267B2

公开(公告)日：2005-09-20

申请号：US09853591

申请日：2001-05-14

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0292 ,  H01L27/0285

摘要： The present invention relates an electrostatic discharge (ESD) protection device that is applied to a mixed voltage circuit assembly. The device comprises a RC controlled circuit subassembly and a field transistor, which the RC controlled circuit is coupled with the mixed voltage circuit assembly to substantially control the ESD protection device to be ON or OFF. The field transistor is coupled between a first power supply and a second power supply of said mixed voltage circuit assembly, which is off on the condition of a normal operating condition and is conducting as an ESD event occurred.

摘要翻译： 本发明涉及一种应用于混合电压电路组件的静电放电（ESD）保护装置。 该装置包括RC控制电路子组件和场晶体管，RC控制电路与混合电压电路组件耦合，以基本上控制ESD保护装置的导通或截止。 场晶体管耦合在所述混合电压电路组件的第一电源和第二电源之间，所述第二电源在正常工作条件下处于关断状态，并且当ESD事件发生时导通。

公开(公告)号：US06933540B2

公开(公告)日：2005-08-23

申请号：US10606922

申请日：2003-06-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H01L27/02 ,  H01L29/72

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.

摘要翻译： 用于双极性输入焊盘的ESD保护装置包括形成有第一，第二和第三区域以形成SCR结构的三阱。 在第一区域上形成有相反导电类型的第一和第二接地连接区域，在第三区域中形成相反导电类型的第一和第二输入连接区域，跨越第二区域形成桥接区域并延伸到 第一和第三区域。 在正常操作下，第一，第二和第三区域形成两个背对背二极管。 在正极性ESD事件下，在桥与第一区之间发生击穿，从而触发用于正极性ESD保护的SCR电路。 在负极性ESD事件下，桥和第三区之间发生击穿，从而触发用于负极性ESD保护的SCR电路。

公开(公告)号：US07193274B2

公开(公告)日：2007-03-20

申请号：US10854792

申请日：2004-05-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

摘要翻译： 在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制 电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。 基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

公开(公告)号：US20060273399A1

公开(公告)日：2006-12-07

申请号：US11496490

申请日：2006-08-01

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L23/62

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

公开(公告)号：US06661273B1

公开(公告)日：2003-12-09

申请号：US10225160

申请日：2002-08-22

申请人： Chun-Hsiang Lai ,  Meng-Huang Liu ,  Shin Su ,  Tao-Cheng Lu

发明人： Chun-Hsiang Lai ,  Meng-Huang Liu ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H03K508

CPC分类号： H01L27/0277 ,  H03K5/08

摘要： A substrate pump circuit and method for I/O ESD protection including NMOS fingers connected to the interconnection between an I/O pad and an internal circuit comprises a MOS device connected to the interconnection between the I/O pad and the internal circuit and the substrate under the control of a switch to turn it on to conduct a pumping current through the substrate resistor when the I/O pad is under ESD stress, so as to pull up the potential of the substrate adjacent to the NMOS fingers, resulting in the reduction of the triggering voltage of the NMOS fingers.

摘要翻译： 用于I / O ESD保护的衬底泵电路和方法，包括连接到I / O焊盘和内部电路之间的互连的NMOS指状包括连接到I / O焊盘和内部电路与衬底之间的互连的MOS器件 在I / O焊盘处于ESD应力下时，在开关控制下将其导通以通过衬底电阻器进行泵浦电流，从而上升与NMOS指状物相邻的衬底的电位，从而减少 的NMOS手指的触发电压。