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公开(公告)号：US08056503B2
公开(公告)日：2011-11-15
申请号：US10483251
申请日：2002-07-02
申请人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
发明人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
CPC分类号： H01J37/32724 , C23C16/45565 , C23C16/509 , C23C16/5096 , H01J37/32082 , H01J37/32174 , H01J37/3244 , H01J37/32532 , H01J37/32623 , H01J37/32642 , H01J37/32715 , H01J37/3411 , H01J2237/002 , H01J2237/0206 , H01J2237/334 , H01L21/67069
摘要： An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., −400 to −600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
摘要翻译： 蚀刻室1包括聚焦环9，以围绕设置在下电极4上的半导体晶片W.等离子体处理器设置有电位控制DC电源33以控制该聚焦环9的电位，以及 这样构成为向下电极4提供例如-400至-600V的DC电压以控制聚焦环9的电位。这种结构防止表面电弧沿着待处理基板的表面发展 。
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公开(公告)号：US08387562B2
公开(公告)日：2013-03-05
申请号：US13242851
申请日：2011-09-23
申请人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
发明人： Akihiro Kikuchi , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
CPC分类号： H01J37/32724 , C23C16/45565 , C23C16/509 , C23C16/5096 , H01J37/32082 , H01J37/32174 , H01J37/3244 , H01J37/32532 , H01J37/32623 , H01J37/32642 , H01J37/32715 , H01J37/3411 , H01J2237/002 , H01J2237/0206 , H01J2237/334 , H01L21/67069
摘要： An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., −400 to −600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
摘要翻译： 蚀刻室1包括聚焦环9，以围绕设置在下电极4上的半导体晶片W.等离子体处理器设置有电位控制DC电源33以控制该聚焦环9的电位，以及 这样构成为向下电极4提供例如-400至-600V的DC电压以控制聚焦环9的电位。这种结构防止表面电弧沿着待处理基板的表面发展 。
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公开(公告)号：US20120006492A1
公开(公告)日：2012-01-12
申请号：US13242851
申请日：2011-09-23
申请人： Akihiro KIKUCHI , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
发明人： Akihiro KIKUCHI , Satoshi Kayamori , Shinya Shima , Yuichiro Sakamoto , Kimihiro Higuchi , Kaoru Oohashi , Takehiro Ueda , Munehiro Shibuya , Tadashi Gondai
IPC分类号： C23F1/08
CPC分类号： H01J37/32724 , C23C16/45565 , C23C16/509 , C23C16/5096 , H01J37/32082 , H01J37/32174 , H01J37/3244 , H01J37/32532 , H01J37/32623 , H01J37/32642 , H01J37/32715 , H01J37/3411 , H01J2237/002 , H01J2237/0206 , H01J2237/334 , H01L21/67069
摘要： An etching chamber 1 incorporates a focus ring 9 so as to surround a semiconductor wafer W provided on a lower electrode 4. The plasma processor is provided with an electric potential control DC power supply 33 to control the electric potential of this focus ring 9, and so constituted that the lower electrode 4 is supplied with a DC voltage of, e.g., −400 to −600 V to control the electric potential of the focus ring 9. This constitution prevents surface arcing from developing along the surface of a substrate to be processed.
摘要翻译： 蚀刻室1包括聚焦环9，以围绕设置在下电极4上的半导体晶片W.等离子体处理器设置有电位控制DC电源33以控制该聚焦环9的电位，以及 这样构成为向下电极4提供例如-400至-600V的DC电压以控制聚焦环9的电位。这种结构防止表面电弧沿着待处理基板的表面发展 。
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