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公开(公告)号：US09064803B2
公开(公告)日：2015-06-23
申请号：US13189964
申请日：2011-07-25
申请人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
IPC分类号： H01L21/28 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11517 , H01L21/28273 , H01L29/42328 , H01L29/513
摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
摘要翻译： 分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。 实施例包括具有包含低k和高k层的电介质间隔物的存储单元。 其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。
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公开(公告)号：US20130032869A1
公开(公告)日：2013-02-07
申请号：US13197367
申请日：2011-08-03
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.
摘要翻译： 分离栅极存储单元被制造成具有在具有沟道区的衬底的上表面下方延伸的字栅。 一个实施例包括提供一个频带工程通道，其中字门延伸到那里。 另一个实施例包括形成掩埋通道，其中字门延伸到掩埋通道下方。
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3.发明授权Method and device for a split-gate flash memory with an extended word gate below a channel region 有权具有在通道区域下方的扩展字门的分闸式闪存的方法和装置公开(公告)号：US08999828B2
公开(公告)日：2015-04-07
申请号：US13197367
申请日：2011-08-03
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792
CPC分类号： H01L29/7881 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel.
摘要翻译： 分离栅极存储单元被制造成具有在具有沟道区的衬底的上表面下方延伸的字栅。 一个实施例包括提供一个频带工程通道，其中字门延伸到那里。 另一个实施例包括形成掩埋通道，其中字门延伸到掩埋通道下方。
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公开(公告)号：US08803122B2
公开(公告)日：2014-08-12
申请号：US13562641
申请日：2012-07-31
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/124 , H01L45/126 , H01L45/144 , H01L45/1691
摘要： Phase-change memory structures are formed with ultra-thin heater liners and ultra-thin phase-change layers, thereby increasing heating capacities and lowering reset currents. Embodiments include forming a first interlayer dielectric (ILD) over a bottom electrode, removing a portion of the first ILD, forming a cell area, forming a u-shaped heater liner within the cell area, forming an interlayer dielectric structure within the u-shaped heater liner, the interlayer dielectric structure including a protruding portion extending above a top surface of the first ILD, forming a phase-change layer on side surfaces of the protruding portion and/or on the first ILD surrounding the protruding portion, and forming a dielectric spacer surrounding the protruding portion.
摘要翻译： 相变存储器结构由超薄加热器衬垫和超薄相变层形成，从而增加加热容量并降低复位电流。 实施例包括在底部电极上形成第一层间电介质（ILD），去除第一ILD的一部分，形成电池区域，在电池区域内形成u形加热器衬垫，在U形形状内形成层间电介质结构 所述层间电介质结构包括在所述第一ILD的顶表面上方延伸的突出部分，在所述突出部分的侧表面和/或围绕所述突出部分的所述第一ILD上形成相变层，以及形成电介质 围绕突出部分的间隔物。
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公开(公告)号：US08536558B1
公开(公告)日：2013-09-17
申请号：US13562646
申请日：2012-07-31
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L47/00
CPC分类号： H01L45/146 , H01L45/04 , H01L45/124 , H01L45/1683
摘要： Resistive random-access memory (RRAM) structures are formed with ultra-thin RRAM-functional layers, thereby improving memory margins. Embodiments include forming an interlayer dielectric (ILD) over a bottom electrode, forming a sacrificial layer over the ILD, removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area, forming a metal layer within the cell area, forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer, removing the sacrificial layer, forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure, and forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.
摘要翻译： 电阻随机存取存储器（RRAM）结构由超薄的RRAM功能层组成，从而提高存储容量。 实施例包括在底部电极上形成层间电介质（ILD），在ILD上形成牺牲层，去除ILD的一部分和与ILD的部分垂直邻接的部分牺牲层，形成细胞区域，形成细胞区域 在所述电池区域内的金属层，在所述金属层的上方或之上形成层间电介质结构，所述层间电介质结构与所述牺牲层的顶表面共平面，去除所述牺牲层，形成 在层间电介质结构的ILD和/或侧表面上的存储层，以及形成围绕至少一部分层间电介质结构的电介质层。
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公开(公告)号：US20130037877A1
公开(公告)日：2013-02-14
申请号：US13206780
申请日：2011-08-10
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , G11C16/0425 , G11C16/14 , G11C16/26 , H01L21/28273 , H01L29/42328 , H01L29/66795 , H01L29/66825 , H01L29/7851 , H01L29/7881
摘要： A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.
摘要翻译： 在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。 实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。
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公开(公告)号：US20130026552A1
公开(公告)日：2013-01-31
申请号：US13189964
申请日：2011-07-25
申请人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
发明人： Eng Huat Toh , Shyue Seng (Jason) Tan , Elgin Quek
IPC分类号： H01L21/28 , H01L29/788
CPC分类号： H01L27/11517 , H01L21/28273 , H01L29/42328 , H01L29/513
摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
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公开(公告)号：US20120292735A1
公开(公告)日：2012-11-22
申请号：US13112317
申请日：2011-05-20
CPC分类号： H01L29/0653 , H01L21/76224 , H01L21/76232 , H01L21/823481 , H01L27/088
摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.
摘要翻译： 形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。 实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。 实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。
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9.发明申请BURIED CHANNEL FINFET SONOS WITH IMPROVED P/E CYCLING ENDURANCE 审中-公开带有改进的P / E循环保护的BURIED CHANNEL FINFET SONOS公开(公告)号：US20120217467A1
公开(公告)日：2012-08-30
申请号：US13034256
申请日：2011-02-24
申请人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
发明人： Shyue Seng (Jason) Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/06 , H01L27/12 , H01L21/762
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/40117 , H01L29/42352 , H01L29/66833 , H01L29/785
摘要： A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer.
摘要翻译： 鳍FET SONOS器件形成有全掩埋沟道。 实施例包括在n型硅层上顺序地形成从第一氧化物层突出的p型硅散热片，在鳍的暴露表面上的n型硅层，第二氧化物层，氮化物层和第三氧化物层 ，以及第三氧化物层上的多晶硅层。 实施例包括蚀刻硅层以形成翅片并在硅层上形成氧化物。 不同的实施例包括：蚀刻BOX层上的硅层以形成翅片; 形成具有圆形顶表面的翅片; 以及在BOX层上形成由n型硅层，第一氧化物层，氮化物层，第二氧化物层和多晶硅层围绕的纳米线。
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