公开(公告)号：US09064803B2

公开(公告)日：2015-06-23

申请号：US13189964

申请日：2011-07-25

申请人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/513

摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

摘要翻译： 分离栅极存储单元由在栅极和存储器栅极堆叠之间的包含高k材料的介电隔离器制造。 实施例包括具有包含低k和高k层的电介质间隔物的存储单元。 其他实施例包括在字门和存储器栅叠层之间具有气隙的存储单元。

公开(公告)号：US08536558B1

公开(公告)日：2013-09-17

申请号：US13562646

申请日：2012-07-31

申请人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L47/00

CPC分类号： H01L45/146 ,  H01L45/04 ,  H01L45/124 ,  H01L45/1683

摘要： Resistive random-access memory (RRAM) structures are formed with ultra-thin RRAM-functional layers, thereby improving memory margins. Embodiments include forming an interlayer dielectric (ILD) over a bottom electrode, forming a sacrificial layer over the ILD, removing a portion of the ILD and a portion of the sacrificial layer vertically contiguous with the portion of the ILD, forming a cell area, forming a metal layer within the cell area, forming an interlayer dielectric structure above or surrounded by and protruding above the metal layer, a top surface of the interlayer dielectric structure being coplanar with a top surface of the sacrificial layer, removing the sacrificial layer, forming a memory layer on the ILD and/or on side surfaces of the interlayer dielectric structure, and forming a dielectric layer surrounding at least a portion of the interlayer dielectric structure.

摘要翻译： 电阻随机存取存储器（RRAM）结构由超薄的RRAM功能层组成，从而提高存储容量。 实施例包括在底部电极上形成层间电介质（ILD），在ILD上形成牺牲层，去除ILD的一部分和与ILD的部分垂直邻接的部分牺牲层，形成细胞区域，形成细胞区域 在所述电池区域内的金属层，在所述金属层的上方或之上形成层间电介质结构，所述层间电介质结构与所述牺牲层的顶表面共平面，去除所述牺牲层，形成 在层间电介质结构的ILD和/或侧表面上的存储层，以及形成围绕至少一部分层间电介质结构的电介质层。

公开(公告)号：US20130037877A1

公开(公告)日：2013-02-14

申请号：US13206780

申请日：2011-08-10

申请人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7881

摘要： A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

摘要翻译： 在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。 实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。

公开(公告)号：US20130026552A1

公开(公告)日：2013-01-31

申请号：US13189964

申请日：2011-07-25

申请人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

发明人： Eng Huat Toh ,  Shyue Seng (Jason) Tan ,  Elgin Quek

IPC分类号： H01L21/28 ,  H01L29/788

CPC分类号： H01L27/11517 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/513

摘要： A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

公开(公告)号：US20120217467A1

公开(公告)日：2012-08-30

申请号：US13034256

申请日：2011-02-24

申请人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng (Jason) Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/06 ,  H01L27/12 ,  H01L21/762

CPC分类号： H01L29/792 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/785

摘要： A Fin FET SONOS device is formed with a full buried channel. Embodiments include forming p-type silicon fins protruding from a first oxide layer, an n-type silicon layer over exposed surfaces of the fins, a second oxide layer, a nitride layer, and a third oxide layer sequentially on the n-type silicon layer, and a polysilicon layer on the third oxide layer. Embodiments include etching a silicon layer to form the fins and forming the oxide on the silicon layer. Different embodiments include: etching a silicon layer on a BOX layer to form the fins; forming the fins with a rounded top surface; and forming nano-wires surrounded by an n-type silicon layer, a first oxide layer, a nitride layer, a second oxide layer, and a polysilicon layer over a BOX layer.

摘要翻译： 鳍FET SONOS器件形成有全掩埋沟道。 实施例包括在n型硅层上顺序地形成从第一氧化物层突出的p型硅散热片，在鳍的暴露表面上的n型硅层，第二氧化物层，氮化物层和第三氧化物层 ，以及第三氧化物层上的多晶硅层。 实施例包括蚀刻硅层以形成翅片并在硅层上形成氧化物。 不同的实施例包括：蚀刻BOX层上的硅层以形成翅片; 形成具有圆形顶表面的翅片; 以及在BOX层上形成由n型硅层，第一氧化物层，氮化物层，第二氧化物层和多晶硅层围绕的纳米线。

公开(公告)号：US20120292735A1

公开(公告)日：2012-11-22

申请号：US13112317

申请日：2011-05-20

申请人： Shyue Seng (Jason) Tan ,  Ying Keung Leung ,  Elgin Quek

发明人： Shyue Seng (Jason) Tan ,  Ying Keung Leung ,  Elgin Quek

IPC分类号： H01L29/06 ,  H01L29/68 ,  H01L21/31

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/088

摘要： The threshold voltage of parasitic transistors formed at corners of shallow trench isolation regions is increased and mobility decreased by employing a high-K dielectric material. Embodiments include STI regions comprising a liner of a high-K dielectric material extending proximate trench corners. Embodiments also include STI regions having a recess formed in the trench, wherein the recess contains a high-K dielectric material, in the form of a layer or spacer, extending proximate trench corners.

摘要翻译： 形成在浅沟槽隔离区域的角落处的寄生晶体管的阈值电压增加，并且通过使用高K介电材料使迁移率降低。 实施例包括STI区域，其包括在沟槽角附近延伸的高K电介质材料的衬垫。 实施例还包括具有形成在沟槽中的凹部的STI区域，其中凹部包含在沟槽角附近延伸的层或间隔物形式的高K电介质材料。

公开(公告)号：US09362274B2

公开(公告)日：2016-06-07

申请号：US13867684

申请日：2013-04-22

申请人： Eng Huat Toh ,  Elgin Quek

发明人： Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/78

CPC分类号： H01L27/088 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

摘要： A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

公开(公告)号：US08946806B2

公开(公告)日：2015-02-03

申请号：US13189554

申请日：2011-07-24

申请人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek ,  Yanzhe Tang

发明人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek ,  Yanzhe Tang

IPC分类号： H01L29/788 ,  H01L21/336 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115

CPC分类号： H01L27/11568 ,  G11C16/04 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7883

摘要： A device having a substrate prepared with a memory cell region having a memory cell is disclosed. The memory cell includes an access transistor and a storage transistor. The access transistor includes first and second source/drain (S/D) regions and the storage transistor includes first and second storage S/D regions. The access and storage transistors are coupled in series and the second S/D regions being a common S/D region. An erase gate is disposed over the common S/D region. A program gate is disposed over the first storage S/D region. Such an arrangement of the memory cell decouples a program channel and an erase channel.

摘要翻译： 公开了一种具有由具有存储单元的存储单元区制备的衬底的器件。 存储单元包括存取晶体管和存储晶体管。 存取晶体管包括第一和第二源极/漏极（S / D）区域，并且存储晶体管包括第一和第二存储S / D区域。 访问和存储晶体管串联耦合，第二S / D区域是公共S / D区域。 擦除栅极设置在公共S / D区域上。 在第一存储S / D区域上设置有编程门。 存储器单元的这种布置使程序通道和擦除通道分离。

公开(公告)号：US20140070159A1

公开(公告)日：2014-03-13

申请号：US13611817

申请日：2012-09-12

申请人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

发明人： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC分类号： H01L21/02 ,  H01L45/00

CPC分类号： H01L27/2436 ,  H01L27/2445 ,  H01L45/08 ,  H01L45/124 ,  H01L45/146 ,  H01L45/1683

摘要： An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

摘要翻译： 公开了一种STI区域的RRAM，其具有垂直BJT选择器。 实施例包括在衬底中限定STI区域，在衬底中注入掺杂剂以在STI区域底部周围和下方形成第一极性的阱，在STI区域的相对侧上的阱上具有第二极性的带，以及 在基板的表面上的第二极性的每个带的第一极性的有源区域，在有源区上形成硬掩模，去除STI区域顶部以形成空腔，在腔侧和底表面上形成RRAM衬垫， 在空腔中形成顶部电极，去除硬掩模的一部分以在空腔的相对侧上形成间隔物，以及将第二极性的掺杂剂注入远离空腔的每个有效区域的一部分。

公开(公告)号：US09276041B2

公开(公告)日：2016-03-01

申请号：US13423793

申请日：2012-03-19

申请人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

发明人： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC分类号： H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L27/2409 ,  H01L27/2445 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

摘要： Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.

摘要翻译： 本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。 在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极 线和第二位线的可变电阻材料。