公开(公告)号：US20050048731A1

公开(公告)日：2005-03-03

申请号：US10654123

申请日：2003-09-02

申请人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

发明人： Jeffrey Patton ,  Mehrdad Mahanpour ,  Thorsten Kammler ,  David Brown ,  Paul Besser ,  Simon Chan ,  Austin Frenkel

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.

摘要翻译： 因此，提供了形成集成电路和结构的方法。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在半导体衬底中形成浅源极/漏极结。 在栅极周围形成侧壁间隔物。 使用侧壁间隔物在半导体衬底中形成深源极/漏极结。 在形成浅的和深的源极/漏极结之后，在侧壁间隔物上形成硅化间隔物。 在邻近硅化间隔物的深源极/漏极结上形成硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与硅化物的接触。

公开(公告)号：US20060267087A1

公开(公告)日：2006-11-30

申请号：US11229188

申请日：2005-09-15

申请人： Robert Chiu ,  Paul Besser ,  Simon Chan ,  Jeffrey Patton ,  Austin Frenkel ,  Thorsten Kammler ,  Errol Ryan

发明人： Robert Chiu ,  Paul Besser ,  Simon Chan ,  Jeffrey Patton ,  Austin Frenkel ,  Thorsten Kammler ,  Errol Ryan

IPC分类号： H01L29/76

CPC分类号： H01L29/7833 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sidewall spacer. A bottom silicide metal is deposited on the source/drain junction and then a top silicide metal is deposited on the bottom silicide metal. The bottom and top silicide metals are formed into their suicides. A dielectric layer is deposited above the semiconductor substrate and a contact is formed in the dielectric layer to the top silicide.

摘要翻译： 提供集成电路。 在半导体衬底上形成栅极电介质，并且在栅极电介质上形成栅极。 在栅极周围形成侧壁间隔物，并且使用侧壁间隔物在半导体衬底中形成源极/漏极结。 底部硅化物金属沉积在源极/漏极结上，然后顶部硅化物金属沉积在底部的硅化物金属上。 底部和顶部的硅化物金属形成它们的自杀剂。 介电层沉积在半导体衬底的上方，并且在电介质层中形成与顶部硅化物的接触。

公开(公告)号：US20070085149A1

公开(公告)日：2007-04-19

申请号：US11538156

申请日：2006-10-03

申请人： Simon Chan ,  Paul Besser ,  Jeffrey Patton

发明人： Simon Chan ,  Paul Besser ,  Jeffrey Patton

IPC分类号： H01L29/76

CPC分类号： H01L21/324 ,  H01L21/26506 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor substrate to form an early phase of silicide. Implanted shallow source/drain junctions are immediately beneath the silicide. A final phase of the silicide is formed. An interlayer dielectric is above the semiconductor substrate, and contacts are formed to the silicide.

摘要翻译： 提供了具有半导体衬底的集成电路。 栅极电介质位于半导体衬底上，栅极位于栅极电介质上。 金属层在半导体衬底上，金属层与半导体衬底反应形成硅化物的早期阶段。 在硅化物的正下方，注入浅的源极/漏极结。 形成硅化物的最终相。 层间电介质在半导体衬底上方，并且与硅化物形成接触。

公开(公告)号：US20050153496A1

公开(公告)日：2005-07-14

申请号：US10756023

申请日：2004-01-12

申请人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

发明人： Minh Ngo ,  Simon Chan ,  Paul Besser ,  Paul King ,  Errol Ryan ,  Robert Chiu

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/6659 ,  H01L29/665

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition process A silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts are then formed in the interlayer dielectric to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 使用低功率等离子体增强化学气相沉积工艺在栅极周围形成侧壁间隔物。在源极/漏极结和栅极上形成硅化物，并且在半导体衬底上沉积层间电介质。 然后在层间电介质中形成与硅化物的接触。

公开(公告)号：US08381613B2

公开(公告)日：2013-02-26

申请号：US12832636

申请日：2010-07-08

申请人： Peter Revelis ,  Simon Chan ,  Mark Van Ryswyck

发明人： Peter Revelis ,  Simon Chan ,  Mark Van Ryswyck

IPC分类号： G05G1/04

CPC分类号： F16C1/14 ,  F16C2361/45 ,  Y10T74/20438 ,  Y10T74/20612

摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.

摘要翻译： 自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。 另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于 框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动 通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

公开(公告)号：US20120006143A1

公开(公告)日：2012-01-12

申请号：US12832636

申请日：2010-07-08

申请人： Peter REVELIS ,  Simon Chan ,  Mark Van Ryswyck

发明人： Peter REVELIS ,  Simon Chan ,  Mark Van Ryswyck

IPC分类号： F16C1/12

CPC分类号： F16C1/14 ,  F16C2361/45 ,  Y10T74/20438 ,  Y10T74/20612

摘要： A self-adjusting parking brake actuator includes a brake lever that is movable between brake-released and brake-applied positions. In addition, the parking brake cable adjust system includes a self-adjustment assembly having a frame; a rack mounted for movement relative to the frame along a longitudinal direction of the rack in a tension direction and an opposite direction; a cable connector for operatively connecting the rack to a brake cable, a first resilient member biasing the rack relative to the frame along its longitudinal direction in the tensioning direction, a primary locking device configured to engage the rack and permit movement of the rack relative to the frame in the tensioning direction only; a secondary locking device moveable between (a) a locking to lock the primary locking device to prevent adjusting movement of the rack relative to the frame in the tensioning direction, and (b) a releasing position to permit the primary locking device to allow adjusting movement of the rack relative to the frame in the tensioning direction by the biasing of the resilient member; and a second resilient member biasing the secondary locking device to the locking position.

摘要翻译： 自调节驻车制动器致动器包括可在制动释放和制动施加位置之间移动的制动杆。 另外，驻车制动器电缆调节系统包括具有框架的自调节组件; 安装用于沿张紧方向和相反方向沿着所述齿条的纵向方向相对于所述框架移动的齿条; 电缆连接器，用于将机架可操作地连接到制动电缆;第一弹性构件，其沿着拉伸方向上的纵向方向相对于框架偏置框架;主锁定装置，构造成接合机架并允许机架相对于 框架仅在张紧方向; 辅助锁定装置可以在（a）锁定以锁定主锁定装置之间移动以防止在张紧方向上调节齿条相对于框架的运动，以及（b）释放位置以允许主锁定装置允许调节运动 通过弹性构件的偏置而相对于框架在张紧方向上的支架; 以及将所述辅助锁定装置偏置到所述锁定位置的第二弹性构件。

公开(公告)号：US20050124170A1

公开(公告)日：2005-06-09

申请号：US10729479

申请日：2003-12-05

申请人： Mario Pelella ,  Simon Chan

发明人： Mario Pelella ,  Simon Chan

IPC分类号： C30B25/18 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L21/31

CPC分类号： H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3043 ,  H01L29/7842

摘要： A method of manufacturing an integrated circuit (IC) can utilizes semiconductor substrate configured in accordance with a trench process. The substrate utilizes trenches in a base layer to induce stress in a layer. The substrate can include silicon. The trenches define pillars on a back side of a bulk substrate or base layer of a semiconductor-on-insulator (SOI) wafer.

摘要翻译： 集成电路（IC）的制造方法可以利用根据沟槽工艺配置的半导体衬底。 衬底利用基层中的沟槽以在层中引起应力。 衬底可以包括硅。 沟槽在绝缘体上半导体（SOI）晶片的体基板或基底层的背侧上限定支柱。

公开(公告)号：US6043153A

公开(公告)日：2000-03-28

申请号：US937915

申请日：1997-09-25

申请人： Takeshi Nogami ,  Simon Chan

发明人： Takeshi Nogami ,  Simon Chan

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76841

摘要： A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the copper layer; and providing a layer disposed above the copper layer. In another aspect, the method and system include providing a copper interconnect formed in a trench on a dielectric. The copper interconnect includes a copper layer disposed in the trench and a layer disposed above the copper layer. The copper layer has a bamboo structure at least one grain. The at least one grain has substantially one orientation.

摘要翻译： 公开了一种用于在形成在电介质中的沟槽中提供铜互连的系统和方法。 一方面，所述方法和系统包括提供铜层; 去除所述沟槽外部的所述铜层的一部分; 退火铜层; 并提供设置在铜层之上的层。 在另一方面，该方法和系统包括提供形成在电介质上的沟槽中的铜互连。 铜互连包括设置在沟槽中的铜层和设置在铜层上方的层。 铜层至少有一颗竹结构。 至少一个颗粒具有基本上一个取向。

公开(公告)号：US08735960B2

公开(公告)日：2014-05-27

申请号：US12313134

申请日：2008-11-17

申请人： Minh Q. Tran ,  Minh-Van Ngo ,  Alexander H. Nickel ,  Sung Jin Kim ,  Simon Chan ,  Ning Cheng

发明人： Minh Q. Tran ,  Minh-Van Ngo ,  Alexander H. Nickel ,  Sung Jin Kim ,  Simon Chan ,  Ning Cheng

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L23/485 ,  H01L29/66825 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.

摘要翻译： 紫外线吸收剂氮氧化硅层覆盖包括一对源极/漏极，栅极绝缘体，浮动栅极，电介质层和控制栅极的存储单元。 导电体通过硅氧氮化物层设置，用于与控制栅极电连接，并且另一个导体通过氧氮化硅层设置，用于电连接到源极/漏极。

公开(公告)号：US08618354B2

公开(公告)日：2013-12-31

申请号：US12898216

申请日：2010-10-05

申请人： Simon Chan ,  Ravi Maruthachalam

发明人： Simon Chan ,  Ravi Maruthachalam

IPC分类号： C12N15/82 ,  A01H5/10 ,  C12N15/29 ,  C12N15/62 ,  C07K14/415 ,  A01H1/08

CPC分类号： A01H1/08 ,  A01H1/02 ,  C07K14/415 ,  C12N15/8241 ,  C12N15/8261 ,  C12N15/8287 ,  Y02A40/146

摘要： Methods and compositions for generating haploid organisms are described.