公开(公告)号：US20160021734A1

公开(公告)日：2016-01-21

申请号：US14332372

申请日：2014-07-15

申请人： Sunaina Srivastava ,  Raza Imam ,  Gagan Kansal ,  Sumit Varshney

发明人： Sunaina Srivastava ,  Raza Imam ,  Gagan Kansal ,  Sumit Varshney

IPC分类号： H05K1/02 ,  H01L23/552 ,  H01L23/00 ,  H01L23/64

CPC分类号： H01L24/48 ,  H01L23/4952 ,  H01L23/552 ,  H01L23/64 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0612 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.

摘要翻译： 半导体器件具有多线引线和具有多位置接合焊盘的管芯。 屏蔽线和防护线都从多线引线延伸到多位置接合焊盘。 屏蔽线（或导线）通过同时传输与多线引线多点接合焊盘之间的防护线相同的信号，为防护线提供有源屏蔽。

公开(公告)号：US09418873B2

公开(公告)日：2016-08-16

申请号：US14467039

申请日：2014-08-24

申请人： Shailesh Kumar ,  Vikas Garg ,  Sumit Varshney ,  Chetan Verma

发明人： Shailesh Kumar ,  Vikas Garg ,  Sumit Varshney ,  Chetan Verma

IPC分类号： H01L23/48 ,  H01L23/12 ,  H01G2/14 ,  H01L21/50 ,  H01L23/522 ,  H01L23/495

CPC分类号： H01L21/50 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/5223 ,  H01L2224/05553 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

摘要翻译： 半导体器件具有在备用高速接口之间共享的片上去耦电容器。 电容焊盘连接到去耦电容器，内部连接焊盘分别连接到备用接口。 内部连接接合线通过电容焊盘和内部连接焊盘将去耦电容器连接到选定的接口，与将器件连接到器件的外部电触点相同。

公开(公告)号：US20160056099A1

公开(公告)日：2016-02-25

申请号：US14467039

申请日：2014-08-24

申请人： Shailesh Kumar ,  Vikas Garg ,  Sumit Varshney ,  Chetan Verma

发明人： Shailesh Kumar ,  Vikas Garg ,  Sumit Varshney ,  Chetan Verma

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L21/50 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/5223 ,  H01L2224/05553 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device has an on-die decoupling capacitor that is shared between alternative high-speed interfaces. A capacitance pad is connected to the decoupling capacitor and internal connection pads are connected respectively to the alternative interfaces. Internal connection bond wires connect the decoupling capacitor to the selected interface through the capacitance pad and the internal connection pads in the same process as connecting the die to external electrical contacts of the device.

摘要翻译： 半导体器件具有在备用高速接口之间共享的片上去耦电容器。 电容焊盘连接到去耦电容器，内部连接焊盘分别连接到备用接口。 内部连接接合线通过电容焊盘和内部连接焊盘将去耦电容器连接到选定的接口，与将器件连接到器件的外部电触点相同。

公开(公告)号：US09271390B2

公开(公告)日：2016-02-23

申请号：US14332372

申请日：2014-07-15

申请人： Sunaina Srivastava ,  Raza Imam ,  Gagan Kansal ,  Sumit Varshney

发明人： Sunaina Srivastava ,  Raza Imam ,  Gagan Kansal ,  Sumit Varshney

IPC分类号： H01L23/48 ,  H01L23/52 ,  H05K1/02 ,  H01L23/64 ,  H01L23/552 ,  H01L23/00

CPC分类号： H01L24/48 ,  H01L23/4952 ,  H01L23/552 ,  H01L23/64 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0612 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/85399

摘要： A semiconductor device has a multi-wire lead and a die having a multi-site bond pad. A shielding wire and a guarded wire both extend from the multi-wire lead to the multi-site bond pad. The shielding wire (or wires) provide active shielding to the guarded wire by simultaneously transmitting the same signal as the guarded wire between the multi-wire lead the multi-site bond pad.

摘要翻译： 半导体器件具有多线引线和具有多位置接合焊盘的管芯。 屏蔽线和防护线都从多线引线延伸到多位置接合焊盘。 屏蔽线（或导线）通过同时传输与多线引线多点接合焊盘之间的防护线相同的信号，为防护线提供有源屏蔽。

公开(公告)号：US09147656B1

公开(公告)日：2015-09-29

申请号：US14328711

申请日：2014-07-11

申请人： Sumit Varshney ,  Rishi Bhooshan ,  Meng Kong Lye ,  Chetan Verma

发明人： Sumit Varshney ,  Rishi Bhooshan ,  Meng Kong Lye ,  Chetan Verma

IPC分类号： H01L23/495 ,  H01L23/552 ,  H01L23/522

CPC分类号： H01L23/49558 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A shielding structure for use with semiconductor devices. The shielding structure has a base with fingers that are sized and shaped to extend within the space between pairs of adjacent leads. The base extends within the space between the die flag and the leads. The shielding structure is further connected to one of the grounded leads.

摘要翻译： 一种用于半导体器件的屏蔽结构。 屏蔽结构具有带指状物的基座，其尺寸和形状被设计成在相邻引线对之间的空间内延伸。 基座在芯片标记和引线之间的空间内延伸。 屏蔽结构进一步连接到一个接地引线。