Covering apparatuses for prevention of bed bug intrusion with leg extension, and methods of use thereof
    1.
    发明授权
    Covering apparatuses for prevention of bed bug intrusion with leg extension, and methods of use thereof 失效
    用于防止病床侵入腿部伸展的覆盖装置及其使用方法

    公开(公告)号:US08256044B1

    公开(公告)日:2012-09-04

    申请号:US13305798

    申请日:2011-11-29

    IPC分类号: A47C29/00

    CPC分类号: A47C29/006

    摘要: A bed covering apparatus that prevents bed bugs from intrusion to an enclosed sleeping area, wherein the bed covering apparatus has a net for exclusion of insects and an openable section disposed at one end of the net that is dimensioned to accommodate legs of a person sleeping within the net, and also contains at least one slippery section to which bed bugs cannot adhere, thereby causing the bed bugs to fall from the netted sleeping area before they have an opportunity to enter the sleeping enclosure. The bed covering apparatus further may comprise straps to securely attach it to a mattress.

    摘要翻译: 一种防止臭虫入侵到封闭的睡眠区域的床罩装置,其中床罩装置具有用于排除昆虫的网和设置在网的一端的可开启部分,其尺寸适于容纳睡在其中的人的腿部 并且还包含至少一个滑动部分,床上的臭虫不能粘附在该部分上,从而在睡眠区域有机会进入睡眠外壳之前导致床上的臭虫掉落。 床罩装置还可以包括用于将其牢固地附接到床垫的带子。

    Covering apparatuses for prevention of bed bug intrusion and methods of use thereof
    2.
    发明授权
    Covering apparatuses for prevention of bed bug intrusion and methods of use thereof 有权
    防止虫虫侵入的覆盖装置及其使用方法

    公开(公告)号:US08087110B1

    公开(公告)日:2012-01-03

    申请号:US13101342

    申请日:2011-05-05

    IPC分类号: A47C29/00

    CPC分类号: A47C29/006 Y10S5/926

    摘要: A bed covering apparatus that prevents bed bugs from intrusion to an enclosed sleeping area, wherein the bed covering apparatus has a net for exclusion of insects, and also contains at least one slippery section to which bed bugs cannot adhere, thereby causing the bed bugs to fall from the netted sleeping area before they have an opportunity to enter the sleeping enclosure.

    摘要翻译: 一种防止臭虫入侵到封闭的睡眠区域的床罩装置,其中,所述床罩装置具有用于排除昆虫的网,并且还包含至少一个滑动部分,其中臭虫不能粘附到其上,从而导致床虫 在有机会进入睡眠外壳之前,从网络睡眠区域掉下来。

    Fabrication method of T-shaped gate electrode in semiconductor device
    3.
    发明授权
    Fabrication method of T-shaped gate electrode in semiconductor device 失效
    半导体器件中T形栅电极的制作方法

    公开(公告)号:US5970328A

    公开(公告)日:1999-10-19

    申请号:US961407

    申请日:1997-10-30

    摘要: A method for fabricating a T-shaped gate electrode of a high speed semiconductor device such as HEMTs which is applied to high speed logic circuit including low-noise receivers and power amplifiers having a frequency of X-band or more respectively, and MMICs having a frequency of millimeter wave band. Such devices require a short gate length and a large sectional area of the gate pattern. The conventional photolithography techniques are in need of the resolution for fabricating a fine line width. Therefore, electron-beam lithography is most widely used. But, it is difficult to enhance throughput in manufacturing semiconductor devices because a lot of exposure time is required in the methods using electron beams. In the present invention, a silicon oxide film or a silicon nitride film is deposited on a mono-layered resist pattern. A dummy pattern corresponding to a leg of the gate is formed using the silicon oxide film or the silicon nitride film. A leg of the gate electrode is formed at the portion of the dummy pattern. According to the present invention, a step for improving the resolution is not required, and a gate electrode having a very fine line width of a few hundreds .ANG. can be obtained by regulating the thickness of the silicon nitride film.

    摘要翻译: 一种用于制造诸如HEMT的高速半导体器件的T形栅极的方法,其应用于包括具有X频带或更多频率的低噪声接收机和功率放大器的高速逻辑电路,以及具有 毫米波段的频率。 这样的器件需要栅极长度短和栅极图案的大截面积。 常规的光刻技术需要用于制造细线宽度的分辨率。 因此,电子束光刻被广泛使用。 但是,由于在使用电子束的方法中需要大量的曝光时间,所以难以提高制造半导体器件的吞吐量。 在本发明中,在单层抗蚀剂图案上沉积氧化硅膜或氮化硅膜。 使用氧化硅膜或氮化硅膜形成对应于栅极支脚的虚拟图案。 栅电极的一条腿形成在虚拟图案的部分。 根据本发明,不需要提高分辨率的步骤,并且可以通过调节氮化硅膜的厚度来获得具有几百安培的极细线宽的栅电极。

    Method of fabricating a compound semiconductor device
    4.
    发明授权
    Method of fabricating a compound semiconductor device 失效
    制造化合物半导体器件的方法

    公开(公告)号:US5885847A

    公开(公告)日:1999-03-23

    申请号:US835957

    申请日:1997-04-11

    CPC分类号: H01L27/1443

    摘要: The invention relates to a method of fabricating a compound semiconductor device by forming a first and a second compound semiconductor devices having a plurality of different epitaxial layers on a common semiconductor substrate. The method comprises the steps of sequentially forming a plurality of first epitaxial layers for manufacturing the first compound semiconductor device on the semiconductor substrate; forming a first insulating film pattern for defining an active region of the first compound semiconductor device; etching the plurality of first epitaxial layers using the first insulating film pattern as a mask; forming a second insulating film on the resultant structure; forming a sidewall insulating spacer on the sidewall of the active region of the first compound semiconductor device by dry etching the second insulating film; sequentially forming a plurality of second epitaxial layers for manufacturing the second compound semiconductor device on the portion from which the plurality of first epitaxial layers is etched back; forming each electrode of the first and second compound semiconductor devices; and forming an interconnection electrode interconnecting each electrode of the first and second compound semiconductor devices.

    摘要翻译: 本发明涉及通过在公共半导体衬底上形成具有多个不同外延层的第一和第二化合物半导体器件来制造化合物半导体器件的方法。 该方法包括以下步骤:在半导体衬底上依次形成用于制造第一化合物半导体器件的多个第一外延层; 形成用于限定所述第一化合物半导体器件的有源区的第一绝缘膜图案; 使用第一绝缘膜图案作为掩模蚀刻多个第一外延层; 在所得结构上形成第二绝缘膜; 通过干蚀刻所述第二绝缘膜,在所述第一化合物半导体器件的有源区的侧壁上形成侧壁绝缘间隔物; 在多个第一外延层被回蚀的部分上依次形成用于制造第二化合物半导体器件的多个第二外延层; 形成第一和第二化合物半导体器件的每个电极; 以及形成互连所述第一和第二化合物半导体器件的每个电极的互连电极。

    Method for fabricating T-shaped electrode and metal layer having low
resistance
    5.
    发明授权
    Method for fabricating T-shaped electrode and metal layer having low resistance 失效
    用于制造具有低电阻的T形电极和金属层的方法

    公开(公告)号:US5856232A

    公开(公告)日:1999-01-05

    申请号:US675972

    申请日:1996-07-05

    摘要: A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.

    摘要翻译: 一种制造T形栅电极的方法包括以下步骤:在半导体衬底上形成精细栅极图案; 在其上形成有栅极图案的半导体衬底上形成绝缘层,并在绝缘层上形成平坦化层以使半导体衬底的表面平坦化; 蚀刻平坦化层以暴露绝缘层的顶部; 使用平坦化层作为掩模,各向同性蚀刻绝缘层以露出栅极图案; 蚀刻暴露的栅极图案以选择性地暴露半导体衬底; 沉积栅极金属以覆盖暴露的基板,绝缘层和平坦化层,以形成T形门; 同时除去平坦化层,从而形成T形门金属,生产率提高。

    Benign prostatic hyperplasia treatment device

    公开(公告)号:US11337689B2

    公开(公告)日:2022-05-24

    申请号:US17362993

    申请日:2021-06-30

    IPC分类号: A61B17/04 A61B17/00

    摘要: A benign prostatic hyperplasia treatment device. The benign prostatic hyperplasia treatment device includes: an anchor assembly including a pair of first and second anchors arranged at upper and lower portions of the outer surface of the prostate gland, and a ligature connecting the first and second anchors with each other so that the first and second anchors continuously compress the prostatic tissues to secure the opening of the prostatic urethra; a sheath inserted into the urethra and having a needle, which guides the anchor assembly to be deployed at the prostate gland; a needle manipulation part for manipulating movement of the needle so that the needle is deployed through an end portion of the sheath.

    FISH TRAP
    8.
    发明申请
    FISH TRAP 审中-公开

    公开(公告)号:US20170231206A1

    公开(公告)日:2017-08-17

    申请号:US15504497

    申请日:2015-08-20

    申请人: Chun Sun PARK

    发明人: Chun Sun PARK

    IPC分类号: A01K69/10 A01K61/95

    CPC分类号: A01K69/10 A01K61/95 A01K69/06

    摘要: A fish trap includes: a fish trap mesh formed with at least one entrance; at least one frame supporting the fish trap mesh; at least one luring part formed to extend from the entrance of the fish trap mesh in a direction toward the inside of the frame and including a lure opening; and an escape prevention part forming an isolated space and provided with at least one fish passage hole through which fish passes after passing through the luring opening of the at least one luring part.