利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

85 条记录 (耗时 0.02 秒)

    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same
    1.
    发明授权
    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
    形成硬掩模的方法和使用其形成半导体器件的精细图案的方法

    公开(公告)号：US08278221B2

    公开(公告)日：2012-10-02

    申请号：US13181655

    申请日：2011-07-13

    申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    IPC分类号： H01L21/331

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

    摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

    Semiconductor memory devices including diagonal bit lines
    2.
    发明授权
    Semiconductor memory devices including diagonal bit lines 有权
    半导体存储器件包括对角位线

    公开(公告)号：US08013375B2

    公开(公告)日：2011-09-06

    申请号：US12465234

    申请日：2009-05-13

    申请人： Duo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Duo-Hoon Goo ,  Han-Ku Cho ,  Joo-Tac Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.

    摘要翻译： 半导体存储器件可以包括具有多个有源区的半导体衬底，其中每个有源区具有在第一轴的方向上的长度和在第二轴的方向上的宽度。 长度可以大于宽度，并且多个有源区域可以在第二轴线的方向上以多个列设置。 可以在衬底上提供多个字线对，其中每个字线对跨越相应的有效区域列的有源区域，在相应字线对的字线之间限定每个有效区域的漏极部分。 衬底上的多个位线可以跨越多个字线对，每个位线电耦合到每列的相应有源区的漏极部分，并且每个位线在不同方向上与相邻列的有源区域的漏极部分交叉 使得相同位线的不同部分在相邻列的不同有效区域上在不同方向上对准。

    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same
    3.
    发明授权
    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
    形成硬掩模的方法和使用其形成半导体器件的精细图案的方法

    公开(公告)号：US08003543B2

    公开(公告)日：2011-08-23

    申请号：US12759771

    申请日：2010-04-14

    申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

    摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

    Semiconductor Memory Devices Including Extended Memory Elements
    5.
    发明申请
    Semiconductor Memory Devices Including Extended Memory Elements 审中-公开
    包括扩展内存元素的半导体存储器件

    公开(公告)号：US20090218654A1

    公开(公告)日：2009-09-03

    申请号：US12465261

    申请日：2009-05-13

    申请人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    发明人： Don-Hoon Goo ,  Han-Ku Cho ,  Joo-Tae Moon ,  Sang-Gyun Woo ,  Gi-Sung Yeo ,  Kyoung-Yun Baek

    IPC分类号： H01L29/06 ,  H01L29/68

    CPC分类号： H01L27/10814 ,  H01L27/0207 ,  H01L27/10882 ,  H01L27/11502

    摘要： A semiconductor memory device may include a semiconductor substrate having an active region thereof, and the active region may have a length and a width, with the length being greater than the width. A field isolation layer may be on the semiconductor substrate surrounding the active region. First and second wordlines may be on the substrate crossing the active region, with the first and second wordlines defining a drain portion of the active region between the first and second wordlines and first and second source portions of the active region at opposite ends of the active region. First and second memory storage elements may be respectively coupled to the first and second source portions of the active region, with the first and second wordlines being between portions of the respective first and second memory storage elements and the active region in a direction perpendicular to a surface of the substrate.

    摘要翻译： 半导体存储器件可以包括具有其有源区的半导体衬底，并且有源区可以具有长度和宽度，其长度大于宽度。 场隔离层可以在围绕有源区的半导体衬底上。 第一和第二字线可以在与有源区交叉的衬底上，其中第一和第二字线限定在第一和第二字线之间的有源区的漏极部分和有源区的第一和第二源极部分在有源区域的相对端处 地区。 第一和第二存储器存储元件可以分别耦合到有源区域的第一和第二源极部分，其中第一和第二字线在相应的第一和第二存储器存储元件的部分之间，并且有源区域在垂直于 基板的表面。

    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE
    6.
    发明申请
    METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE 失效
    形成半导体器件精细图案的方法

    公开(公告)号：US20080206686A1

    公开(公告)日：2008-08-28

    申请号：US11781987

    申请日：2007-07-24

    申请人： Doo-youl LEE ,  Han-ku CHO ,  Suk-joo LEE ,  Gi-sung YEO ,  Pan-suk KWAK ,  Min-jong HONG

    发明人： Doo-youl LEE ,  Han-ku CHO ,  Suk-joo LEE ,  Gi-sung YEO ,  Pan-suk KWAK ,  Min-jong HONG

    IPC分类号： G03C5/00

    CPC分类号： H01L21/0337

    摘要： A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

    摘要翻译： 在半导体衬底上形成精细图案的方法包括形成包括具有特征尺寸F和任意间距P的第一线图案的第一图案，以及形成包括布置在相邻第一线图案之间的第二线图案的第二图案，以形成 具有半间距P / 2的精细图案，第一和第二线图案沿第一方向重复。 在与第一方向垂直的第二方向上的至少一个第一线图案中形成间隙，以通过间隙连接位于第一线图案的每一侧上的第二线图案。 至少一个沿着第一方向延伸的点动图案由与连接的第二线图案相邻的至少一个第一线图案形成。 所述点动图案在所述第二方向上在所连接的第二线图案中的至少一个中形成间隙。

    Semiconductor devices having Fin-type active areas and methods of manufacturing the same
    7.
    发明申请
    Semiconductor devices having Fin-type active areas and methods of manufacturing the same 有权
    具有Fin型有源区的半导体器件及其制造方法

    公开(公告)号：US20080105931A1

    公开(公告)日：2008-05-08

    申请号：US11979748

    申请日：2007-11-08

    申请人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

    发明人： Hyun-jae Kang ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7851 ,  H01L29/66795

    摘要： A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

    摘要翻译： 具有翅片型有源区的半导体器件包括沿着半导体器件的栅电极的方向设置的多个有源区，第一器件隔离层和凹陷的第二器件隔离层。 凹陷的第二器件隔离层和第一器件隔离层设置在栅电极的垂直方向上。 第一器件隔离层和多个有源区交替地设置在多个有源区的第一方向上。

    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same
    8.
    发明申请
    Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same 有权
    形成硬掩模的方法和使用其形成半导体器件的精细图案的方法

    公开(公告)号：US20080090419A1

    公开(公告)日：2008-04-17

    申请号：US11727124

    申请日：2007-03-23

    申请人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    发明人： Cha-won Koh ,  Han-ku Cho ,  Jeong-lim Nam ,  Gi-sung Yeo ,  Joon-soo Park ,  Ji-young Lee

    IPC分类号： H01L21/311

    CPC分类号： H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76816

    摘要： A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

    摘要翻译： 形成硬掩模的方法采用双重图案化技术。 第一硬掩模层形成在基板上，并且通过光刻在第一硬掩模层上形成第一牺牲图案。 第一牺牲图案的特征彼此间隔开第一间距。 然后在第一牺牲图案和第一硬掩模层上共形地形成第二硬掩模层，以便限定第一牺牲图案的相邻特征之间的凹部。 去除第二硬掩模层的上部以露出第一牺牲图案，并且去除暴露的第一牺牲图案和第二牺牲图案。 然后蚀刻第二硬掩模层和第一硬掩模层，以形成由第一硬掩模层和第二硬掩模层的残留部分组成的硬掩模。 可以使用硬掩模作为蚀刻掩模来形成诸如沟槽隔离区域或接触孔图案的半导体器件的精细图案。

    METHOD OF MANUFACTURING A MASK
    10.
    发明申请
    METHOD OF MANUFACTURING A MASK 有权
    制作面膜的方法

    公开(公告)号：US20080010628A1

    公开(公告)日：2008-01-10

    申请号：US11762838

    申请日：2007-06-14

    申请人： Sung-gon Jung ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

    发明人： Sung-gon Jung ,  Ji-young Lee ,  Han-ku Cho ,  Gi-sung Yeo

    IPC分类号： G06F17/50 ,  G03F1/00

    CPC分类号： G03F1/36

    摘要： A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.

    摘要翻译： 一种制造掩模的方法包括：设计第一掩模数据图案，设计用于形成第一掩模数据图案的第二掩模数据图案，使用基于布局的自对准方法获取从第二掩模数据图案预测的第一仿真图案， 对准双重图案（SADP）仿真，将第一仿真模式与第一掩模数据模式进行比较，并根据比较结果修改第二掩模数据模式。 该方法还包括在修改的第二掩模数据模式上执行光学邻近校正（OPC），从使用基于图像的SADP仿真的第二掩模数据模式中获取第二仿真模式，其中已经执行了OPC，并且比较 第二仿真模式和第一掩模数据模式，并且根据比较结果制造对应于已经执行了OPC的第二掩模数据模式的第一掩模层。