公开(公告)号：US20220367286A1

公开(公告)日：2022-11-17

申请号：US17813862

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing, Ltd.

Inventor： Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L21/285

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.

公开(公告)号：US20140213031A1

公开(公告)日：2014-07-31

申请号：US13750883

申请日：2013-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING, LTD.

Inventor： Hung-Ta Lin ,  Meng-Ku Chen ,  Huicheng Chang

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract translation: 一种方法包括凹陷隔离区域，其中隔离区域之间的半导体条的一部分在凹陷隔离区域的顶表面之上，并且形成半导体鳍片。 模拟栅极形成为覆盖半导体鳍片的中间部分。 形成层间电介质（ILD）以覆盖半导体鳍片的端部。 然后去除虚拟栅极以形成第一凹部，其中中间部分暴露于第一凹部。 去除半导体鳍片的中间部分以形成第二凹部。 进行外延以在第二凹部中生长半导体材料，其中半导体材料在端部之间。 栅电介质和栅电极形成在第一凹槽中。 栅极电介质和栅极电极在半导体材料之上。

公开(公告)号：US20140139246A1

公开(公告)日：2014-05-22

申请号：US13681048

申请日：2012-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING, LTD.

Inventor： Mei-Chen Chuang ,  Jui-Cheng Huang

IPC: G01R31/28 ,  H01L23/544

CPC classification number: G01R31/2874 ,  G01K7/015 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes measuring a first voltage across a test diode on a semiconductor wafer while injecting a first current into the test diode, measuring a second voltage across the test diode while injecting a second current into the test diode, and determining temperature of a region proximate the test diode according to difference between the first voltage and the second voltage.

Abstract translation: 一种方法包括测量半导体晶片上的测试二极管上的第一电压，同时向测试二极管注入第一电流，测量跨越测试二极管的第二电压，同时向测试二极管注入第二电流，以及确定接近的区域的温度 测试二极管根据第一电压和第二电压之间的差值。

公开(公告)号：US20130193521A1

公开(公告)日：2013-08-01

申请号：US13750186

申请日：2013-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING, Ltd.

Inventor： Chun-Yi Lee ,  Harry-Hak-Lay Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC: H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

Abstract: A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

Abstract translation: 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

公开(公告)号：US20230268285A1

公开(公告)日：2023-08-24

申请号：US18310743

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing, Ltd.

Inventor： Chih-Chia Hu ,  Chang-Ching Yu ,  Ming-Fa Chen

IPC: H01L23/544 ,  H01L21/56 ,  G03F9/00 ,  G03F7/00 ,  G03F1/00 ,  G03F1/42

CPC classification number: H01L23/544 ,  G03F1/00 ,  G03F1/42 ,  G03F7/70475 ,  G03F7/70633 ,  G03F9/708 ,  H01L21/56 ,  H01L21/60 ,  H01L2223/54426

Abstract: A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.