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    Modular interconnect circuitry for multi-channel transceiver clock signals
    1.
    发明申请
    Modular interconnect circuitry for multi-channel transceiver clock signals 有权
    用于多通道收发器时钟信号的模块化互连电路

    公开(公告)号：US20070018863A1

    公开(公告)日：2007-01-25

    申请号：US11270718

    申请日：2005-11-08

    Applicant: Tim Hoang ,  Sergey Shumarayev

    Inventor： Tim Hoang ,  Sergey Shumarayev

    IPC: H03M9/00

    CPC classification number: G06F1/10 ,  H03K19/177 ,  H03K19/17736

    Abstract: Circuitry for distributing clock signals (e.g., reference clock signals) among a plurality of blocks of circuitry. Each block may include reference clock source circuitry and reference clock utilization circuitry. Each block also preferably includes an identical or substantially identical module of clock signal distribution circuitry that can (1) accept a signal from the source circuitry in that block, (2) apply any of several clock signals to the utilization circuitry in that block, and (3) connect to the similar module(s) of one or more adjacent blocks.

    Abstract translation: 用于在多个电路块之间分配时钟信号（例如，参考时钟信号）的电路。 每个块可以包括参考时钟源电路和参考时钟利用电路。 每个块还优选地包括相同或基本相同的时钟信号分配电路模块，其可以（1）接收来自该块中的源电路的信号，（2）将几个时钟信号中的任何一个应用于该块中的利用电路，以及 （3）连接到一个或多个相邻块的相似模块。

    Methods and apparatus to DC couple LVDS driver to CML levels
    2.
    发明申请
    Methods and apparatus to DC couple LVDS driver to CML levels 有权
    将LVDS驱动程序直接耦合到CML级别的方法和设备

    公开(公告)号：US20060220681A1

    公开(公告)日：2006-10-05

    申请号：US11098832

    申请日：2005-04-04

    Applicant: Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    Inventor： Wilson Wong ,  Tim Hoang ,  Sergey Shumarayev ,  Rakesh Patel ,  Simardeep Maangat

    IPC: H03K19/094

    CPC classification number: H03K19/017545

    Abstract: Circuitry and methods are provided for an LVDS-like transmitter that may be able to DC couple to a receiver having a CML termination scheme. Replacing the common mode voltage source of an LVDS transmitter with a resistive pulldown to ground may allow the transmitter to interface in a DC coupled fashion with a CML receiver. Further, the resistive pulldown may be programmable. This LVDS-like transmitter may be able to support a wider customer base by allowing it to DC couple to a wider range of termination voltage levels, such as CML termination voltage levels.

    Abstract translation: 为能够将DC耦合到具有CML终止方案的接收机的类似LVDS的发射机提供电路和方法。 将具有电阻下拉到地的LVDS发射机的共模电压源替换可允许发射机以直流耦合方式与CML接收器接口。 此外，电阻下拉可以是可编程的。 这种类似LVDS的发射机可能能够通过允许其将DC耦合到更广泛的终止电压电平范围（例如CML终止电压电平）来支持更广泛的客户群。

    Multi-channel communication circuitry for programmable logic device integrated circuits and the like
    3.
    发明申请
    Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
    用于可编程逻辑器件集成电路等的多通道通信电路

    公开(公告)号：US20070058618A1

    公开(公告)日：2007-03-15

    申请号：US11288810

    申请日：2005-11-28

    Applicant: Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    Inventor： Thungoc Tran ,  Sergey Shumarayev ,  Tim Hoang ,  Ning Xue ,  Chong Lee ,  Ramanand Venkata

    IPC: H04L12/50

    CPC classification number: H03K19/17736 ,  H03K19/17744

    Abstract: An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.

    Abstract translation: 诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。 提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作 一起，八个渠道在一起等）。 共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。 电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

    On-chip eye viewer architecture for highspeed transceivers
    8.
    发明授权
    On-chip eye viewer architecture for highspeed transceivers 有权
    用于高速收发器的片上眼睛查看器架构

    公开(公告)号：US08744012B1

    公开(公告)日：2014-06-03

    申请号：US13369108

    申请日：2012-02-08

    Applicant: Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    Inventor： Weiqi Ding ,  Mingde Pan ,  Sergey Shumarayev ,  Peng Li

    IPC: H03K9/00

    CPC classification number: H04L1/203 ,  G01R31/31711

    Abstract: System, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with a serial input signal either during or after equalization. The device may include an equalizer and eye viewer circuitry configured to select a node of the equalizer for eye monitoring of the input signal, which may be during or after equalization. In one embodiment, the eye viewer circuitry may provide a separate sampler for each respective node, while sharing a control logic and phase interpolator among the samplers. The eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the serial input signal, as seen from the selected node of the equalizer.

    Abstract translation: 提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和设备。 例如，集成电路器件的一个实施例可能能够在均衡期间或之后确定与串行输入信号相关联的眼图。 该装置可以包括均衡器和眼睛观察器电路，其被配置为选择均衡器的节点，用于在均衡期间或之后的输入信号的眼睛监视。 在一个实施例中，眼睛观察器电路可以为每个相应节点提供单独的采样器，同时在采样器之间共享控制逻辑和相位插值器。 从均衡器的选定节点看，眼睛观察器电路可以确定与串行输入信号相关联的眼图的水平和垂直边界。

    Simulation tool for high-speed communications links
    9.
    发明授权
    Simulation tool for high-speed communications links 有权
    用于高速通信链接的仿真工具

    公开(公告)号：US08626474B2

    公开(公告)日：2014-01-07

    申请号：US12762848

    申请日：2010-04-19

    Applicant: Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    Inventor： Peng Li ,  Masashi Shimanouchi ,  Thungoc M. Tran ,  Sergey Shumarayev

    IPC: G06F7/60 ,  G06G7/62 ,  G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F2217/10

    Abstract: A link simulation tool for simulating high-speed communications link systems is provided. Communications links may include link subsystems such as transmit (TX) circuitry, receive (TX) circuitry, oscillator circuits that provide reference clock signals to the TX and RX circuitry, and channels that link the TX and RX circuitry. The link simulation tool may model each of the subsystems using behavioral models. The behavioral models may include characteristic functions such as transfer functions, probability density functions, and eye characteristics. The link simulation tool may have a link analysis engine that is capable of performing two-dimensional (two-variable) convolution operations and in applying dual-domain (frequency-time) transformations on the characteristic functions provided by the behavioral models to simulate the performance of the link system. The link simulation tool may have an input screen that allows a user to specify desired link parameters and a data display screen that display simulated results.

    Abstract translation: 提供了一种用于模拟高速通信链路系统的链路仿真工具。 通信链路可以包括链路子系统，例如发射（TX）电路，接收（TX）电路，向TX和RX电路提供参考时钟信号的振荡器电路，以及链接TX和RX电路的信道。 链接仿真工具可以使用行为模型对每个子系统进行建模。 行为模型可以包括特征功能，例如传递函数，概率密度函数和眼睛特征。 链路仿真工具可以具有能够执行二维（双变量）卷积运算并且对由行为模型提供的特征函数应用双域（频率 - 时间）变换以模拟性能的链路分析引擎 的链接系统。 链接仿真工具可以具有允许用户指定期望的链接参数的输入屏幕和显示模拟结果的数据显示屏幕。

    Phase-locked loop architecture and clock distribution system
    10.
    发明授权
    Phase-locked loop architecture and clock distribution system 有权
    锁相环架构和时钟分配系统

    公开(公告)号：US08542042B1

    公开(公告)日：2013-09-24

    申请号：US13532528

    申请日：2012-06-25

    Applicant: Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    Inventor： Tien Duc Pham ,  Sergey Shumarayev ,  Richard G. Cliff

    IPC: H03L7/06

    CPC classification number: H03L7/23 ,  G06F1/10 ,  H03L7/0807 ,  H03L7/183 ,  H03L7/197 ,  H03L7/1974 ,  H04L7/0331

    Abstract: One embodiment relates to a fracture-able PLL circuit. The fracture-able PLL circuit includes a first phase-locked loop circuit generating a first frequency output, a second phase-locked loop circuit; arranged to generate a second frequency output, and a plurality of shared output resources. Reconfigurable circuitry is arranged so that either of the first and second frequency outputs is receivable by each of the plurality of shared output resources. Another embodiment relates to an integrated circuit which includes a plurality of PMA modules, a plurality of multiple-purpose PLL circuits, and a programmable clock network. The programmable clock network is arranged to allow the clock signals output by the multiple-purpose PLL circuits to be selectively used either by the PMA modules for a transceiver application or by other circuitry for a non-transceiver application. Other embodiments and features are also disclosed.

    Abstract translation: 一个实施例涉及一种可断裂的PLL电路。 断裂PLL电路包括产生第一频率输出的第一锁相环电路，第二锁相环电路; 布置成产生第二频率输出和多个共享输出资源。 可重构电路被布置成使得第一和第二频率输出中的任一个可由多个共享输出资源中的每一个接收。 另一实施例涉及一种集成电路，其包括多个PMA模块，多个多用途PLL电路和可编程时钟网络。 可编程时钟网络被布置为允许由多用途PLL电路输出的时钟信号被PMA模块选择性地用于收发器应用或由用于非收发器应用的其它电路。 还公开了其它实施例和特征。

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