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    Semiconductor memory device having flip-flop circuits
    2.
    发明授权
    Semiconductor memory device having flip-flop circuits 失效
    具有触发电路的半导体存储器件

    公开(公告)号：US4291394A

    公开(公告)日：1981-09-22

    申请号：US87389

    申请日：1979-10-22

    申请人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    发明人： Masao Nakano ,  Tomio Nakano ,  Yoshihiro Takemae ,  Katsuhiko Kabashima

    IPC分类号： G11C11/419 ,  G11C5/06 ,  G11C11/409 ,  G11C11/4096 ,  G11C11/4099 ,  H03K3/356 ,  G11C11/40

    CPC分类号： G11C5/063 ,  G11C11/4096 ,  G11C11/4099

    摘要： A semiconductor memory device having flip-flop circuits, in which first and second bit lines are connected to each of the flip-flop circuits as a sense amplifier, the potential of the second bit line being opposite to the potential of the first bit line, and the first and second data bus lines cross perpendicularly to the first and second bit lines, respectively, the first and second dummy lines are arranged in parallel with the first and second data bus lines respectively, in order to prevent erroneous operation of an I/O amplifier connected to the first and second data bus lines.

    摘要翻译： 一种具有触发电路的半导体存储器件，其中第一和第二位线连接到作为读出放大器的每个触发器电路，第二位线的电位与第一位线的电位相反， 并且第一和第二数据总线分别与第一和第二位线垂直交叉，第一和第二虚拟线分别与第一和第二数据总线线并排布置，以防止I / O放大器连接到第一和第二数据总线。

    Semiconductor integrated circuit device having fuse-type information storing circuit
    4.
    发明授权
    Semiconductor integrated circuit device having fuse-type information storing circuit 失效
    具有熔丝型信息存储电路的半导体集成电路装置

    公开(公告)号：US4707806A

    公开(公告)日：1987-11-17

    申请号：US712149

    申请日：1985-03-15

    申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

    IPC分类号： H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

    CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

    摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

    摘要翻译： 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

    Semiconductor integrated circuit device
    7.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4550289A

    公开(公告)日：1985-10-29

    申请号：US453115

    申请日：1982-12-27

    申请人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

    发明人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

    IPC分类号： G01R31/26 ,  G06F11/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  G01R31/28

    CPC分类号： G01R31/26 ,  G06F11/006

    摘要： A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

    摘要翻译： 半导体集成电路（IC）装置包括测试电路。 测试电路用于在测试期间区分电源电平或在位于半导体芯片内部的内部节点处发生地电平。 测试电路包括串联连接的MIS晶体管和MIS二极管。 MIS晶体管的栅极连接到内部节点。 MIS二极管连接到外部输入/输出（I / O）引脚。 可以通过施加到外部I / O引脚的第一电压电平或第二电压电平来区分内部节点的电平，即电源电平或接地电平，无论哪一个使外部电流从外部 I / O引脚。

    Buffer circuit
    9.
    发明授权
    Buffer circuit 失效
    缓冲电路

    公开(公告)号：US4458337A

    公开(公告)日：1984-07-03

    申请号：US354498

    申请日：1982-03-03

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

    IPC分类号： G11C11/413 ,  G11C11/408 ,  H03K3/356 ,  G11C13/00

    CPC分类号： H03K3/356017 ,  H03K3/35606

    摘要： A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.

    摘要翻译： 缓冲电路包括经由第一输入电路接收外部输入的触发器和经由第二输入电路的参考电压。 然后通过输出电路产生内部互补输出。 触发器通过第二输入电路与至少一个电平设置装置协作。 电平设置装置用于产生电压电平，以在触发器激活期间停用第二输入电路。

    Address Buffer
    10.
    发明授权
    Address Buffer 失效
    地址缓冲区

    公开(公告)号：US4451908A

    公开(公告)日：1984-05-29

    申请号：US354499

    申请日：1982-03-03

    申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto ,  Tsutomu Mezawa

    发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto ,  Tsutomu Mezawa

    IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C11/408 ,  G11C11/40

    CPC分类号： G11C11/4082 ,  G11C11/406

    摘要： An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

    摘要翻译： 用于动态存储器的地址缓冲器包括触发器。 触发器在其一个输入/输出端子处与第一输入电路和第三输入电路耦合，第一输入电路和第三输入电路彼此并联并且在其另一输入/输出端与第二输入电路连接。 第二输入电路接收参考电压，并在正常操作模式期间由外部地址定时时钟激活。 第一个输入电路也由外部地址定时时钟激活，但接收一个外部地址。 第三输入电路接收内部刷新地址，并由内部刷新地址激活。 地址缓冲器与产生内部刷新地址定时时钟和外部地址定时时钟的切换器配合，或者通过切换由地址驱动时钟发生器产生的基本定时时钟。