公开(公告)号：US4970693A

公开(公告)日：1990-11-13

申请号：US484474

申请日：1990-02-23

申请人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

发明人： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

IPC分类号： G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

CPC分类号： G11C7/22 ,  G11C8/18

摘要： A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

摘要翻译： 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

公开(公告)号：US4583204A

公开(公告)日：1986-04-15

申请号：US452436

申请日：1982-12-23

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

IPC分类号： G11C11/401 ,  G11C11/4072 ,  G11C11/409 ,  G11C11/417 ,  G11C11/24

CPC分类号： G11C11/4072

摘要： A dynamic semiconductor memory device includes data output lines (D, D), a data output buffer (12), a column enable buffer (9), and an output enable buffer (11) for generating an output enable signal (OE) to enable the transmission of data from the data output lines to the data buffer. The output enable buffer is driven by the clock signals of the column enable buffer. An output disabling circuit (13) is provided to stop the generation of an output enable signal by the output enable buffer when the output enable buffer is not being driven by the column enable buffer. As a result, the data output buffer assumes a high-impedance state when a power supply is turned on.

摘要翻译： 动态半导体存储器件包括数据输出线（D，＆amp; upbar＆D），数据输出缓冲器（12），列使能缓冲器（9）和用于产生输出使能信号（OE）的输出使能信号 使数据从数据输出线传输到数据缓冲区。 输出使能缓冲器由列使能缓冲器的时钟信号驱动。 提供输出禁止电路（13），用于当输出使能缓冲器不被列使能缓冲器驱动时，通过输出使能缓冲器停止产生输出使能信号。 结果，当电源接通时，数据输出缓冲器呈现高阻抗状态。

公开(公告)号：US4550289A

公开(公告)日：1985-10-29

申请号：US453115

申请日：1982-12-27

申请人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

发明人： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

IPC分类号： G01R31/26 ,  G06F11/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  G01R31/28

CPC分类号： G01R31/26 ,  G06F11/006

摘要： A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

摘要翻译： 半导体集成电路（IC）装置包括测试电路。 测试电路用于在测试期间区分电源电平或在位于半导体芯片内部的内部节点处发生地电平。 测试电路包括串联连接的MIS晶体管和MIS二极管。 MIS晶体管的栅极连接到内部节点。 MIS二极管连接到外部输入/输出（I / O）引脚。 可以通过施加到外部I / O引脚的第一电压电平或第二电压电平来区分内部节点的电平，即电源电平或接地电平，无论哪一个使外部电流从外部 I / O引脚。

公开(公告)号：US4450515A

公开(公告)日：1984-05-22

申请号：US388194

申请日：1982-06-14

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/407 ,  H01L21/822 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H02M3/18 ,  H03K3/01

CPC分类号： G05F3/205

摘要： A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

摘要翻译： 公开了一种适用于测量衬底漏电流的偏置电压发生器。 偏置电压发生器包括振荡器，由振荡器经由泵浦电容器驱动的电荷泵浦电路和电荷泵浦开关。 电荷泵开关与充电电路串联。 电荷泵开关与外部电极配合，用于控制电荷泵送电路的导通或关断状态。 通过外部电极变为浮置状态，电荷泵浦开关被切断，并且在上述测量完成并且电路从工厂出货之后用于确保电荷泵开关不可操作的电阻器。

公开(公告)号：US4511997A

公开(公告)日：1985-04-16

申请号：US439507

申请日：1982-11-05

申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

IPC分类号： G11C11/419 ,  G11C11/34 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096

摘要： A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.

摘要翻译： 一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。 提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。 一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号 控制信号线被包括在存储器件中。 所有的读出放大器都具有控制信号线和数据总线。

公开(公告)号：US4532613A

公开(公告)日：1985-07-30

申请号：US356487

申请日：1982-03-09

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Tsuyoshi Ohira

IPC分类号： G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/40

CPC分类号： G11C11/4093

摘要： In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.

摘要翻译： 在包括从存储单元阵列读出的数据信号的输出缓冲电路的半导体存储器件中，输出级MOS晶体管根据输出缓冲电路的输出信号而导通和截止，而输出缓冲器使能（OBE） 信号发生器电路，用于产生用作向输出缓冲电路的输出级的电压供给的OBE信号，提供VBS电压发生器电路，用于产生比OBE上升之前的电压源VCC高的电压VBS 信号，哪个电压VBS被用作到OBE信号发生器电路的输出级的电压供应，由此OBE信号形成为快速上升到高于电压源VCC的电平的电压波形。

公开(公告)号：US4484312A

公开(公告)日：1984-11-20

申请号：US392077

申请日：1982-06-25

申请人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

发明人： Tomio Nakano ,  Masao Nakano ,  Yoshihiro Takemae ,  Norihisa Tsuge ,  Tsuyoshi Ohira

IPC分类号： G11C11/401 ,  G11C11/4099 ,  G11C11/40

CPC分类号： G11C11/4099

摘要： A dynamic random access memory device which comprises one-transistor, one-capacitor-type memory cells (C.sub.00 .about.C.sub.127,127) in rows and columns and dummy cells (DC.sub.20 '.about.DC.sub.2,127 ', DC.sub.20 ".about.DC.sub.2,127 ", DC.sub.20 "'.about.DC.sub.2,127 "') in rows. The capacitors (C.sub.d) of the dummy cells are charged to a high power supply potential (V.sub.CC) by one or more charging transistors (Q.sub.A or Q.sub.A ') clocked by a reset clock signal (.phi..sub.R). The capacitors (C.sub.d) of the dummy cells are discharged to a low power supply potential (V.sub.SS) by one or more transistors (Q.sub.B or Q.sub.B ') clocked by an operation clock signal (.phi..sub.WL) having a potential lower than the high power supply potential (V.sub.CC).

摘要翻译： 一种动态随机存取存储器件，其包括行和列中的单晶体管，单电容器型存储单元（C00 DIFFERENCE C127,127）和虚设单元（DC20'DIFFERENCE DC2,127'，DC20“DIFFERENCE DC2,127” '，DC20'''DIFFERENCE DC2,127'''）。 虚拟单元的电容器（Cd）通过由复位时钟信号（phi R）计时的一个或多个充电晶体管（QA或QA'）充电到高电源电位（VCC）。 虚拟单元的电容器（Cd）由一个或多个晶体管（QB或QB'）放电到低电源电位（VSS），该晶体管（QB或QB'）由具有低于高电源电位的电位的操作时钟信号（phi WL） 电位（VCC）。

公开(公告)号：US4716549A

公开(公告)日：1987-12-29

申请号：US901680

申请日：1986-08-29

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Shigeki Nozaki ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G11C11/407 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/02 ,  G11C11/24

CPC分类号： G11C11/4099 ,  G11C11/4094

摘要： A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

摘要翻译： 一种半导体存储器件，其能够补偿包括存储单元的存储单元和用于将存储单元耦合到位线的门电路的识别电压的变化。 该装置具有用于在复位状态下将位线对预充电到预定的合成预充电电压的预充电电路。 预充电电路对通过在复位状态下将补偿电压加到预充电电压而获得的所得预充电电压对位线对进行预充电。 补偿电压适于基于由于处于活动状态的栅极电路的寄生电容而由字线与存储电容器的电容耦合而引起的存储单元电压的变化来补偿存储单元识别电压的变化，以及 当假设寄生电容不存在时，预充电电压适于优化存储单元识别电压。

公开(公告)号：US4602356A

公开(公告)日：1986-07-22

申请号：US445921

申请日：1982-12-01

申请人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

发明人： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413

CPC分类号： G11C8/18

摘要： A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

摘要翻译： 半导体存储器件以所谓的地址复用存取方式工作。 器件的一部分通过接收行地址选通（＆upbar＆R）信号来使能。 器件的列部分通过在其使能状态期间同时接收列地址选通（＆upbar＆C）信号和从行部分提供的定时控制信号来启用。 列部分中的列地址缓冲器通过同时接收＆upbar＆C信号和定时控制信号而被使能。 定时控制信号从电路产生，当它检测并保持＆amp; R＆R信号。

公开(公告)号：US4504929A

公开(公告)日：1985-03-12

申请号：US444499

申请日：1982-11-24

申请人： Yoshihiro Takemae ,  Tsuyoshi Ohira ,  Seiji Enomoto

发明人： Yoshihiro Takemae ,  Tsuyoshi Ohira ,  Seiji Enomoto

IPC分类号： G11C11/401 ,  G11C11/4091 ,  G11C29/00 ,  G11C29/02 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/026 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A dynamic semiconductor memory device provides a selected real cell, which is connected to a first of a pair of bit lines connected to a sense amplifier, and a dummy cell which is connected to a second of the pair of bit lines so as to perform a read-out operation. The dynamic semiconductor memory cell further provides an active restore circuit for pulling up the bit line potential of the bit line on the higher potential side of the pair of bit lines, in which the potential difference is increased by the read-out operation. The dynamic semiconductor cell can also provide a write-in circuit for charging the selected real cell through the bit line. A test power source pad is provided in the active restore circuit or the write in circuit so that when the reference level of the real cell is tested an optional power source can be applied from the test power source pad instead of from a normal power source.

摘要翻译： 动态半导体存储器件提供选择的实数单元，其连接到连接到读出放大器的一对位线中的第一个，以及连接到所述一对位线中的第二位的虚拟单元，以执行 读出操作。 动态半导体存储单元进一步提供有源恢复电路，用于提升位线对的位线电位，该位线位于通过读出操作增加电位差的位线对的较高电位侧。 动态半导体单元还可以提供用于通过位线对所选择的真实单元进行充电的写入电路。 在有源恢复电路或写入电路中提供测试电源焊盘，使得当测试真实单元的参考电平时，可以从测试电源焊盘而不是普通电源施加可选的电源。