公开(公告)号：US08951840B2

公开(公告)日：2015-02-10

申请号：US14354592

申请日：2012-12-04

申请人： Fei Qin ,  Guofeng Xia ,  Tong An ,  Chengyan Liu ,  Wei Wu ,  Wenhui Zhu

发明人： Fei Qin ,  Guofeng Xia ,  Tong An ,  Chengyan Liu ,  Wei Wu ,  Wenhui Zhu

IPC分类号： H01L21/00 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/4828 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92127 ,  H01L2224/92242 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45664

摘要： A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.

摘要翻译： 提供了一种基于多行四边形扁平无引线（QFN）封装的倒装芯片（FCoC）封装的制造方法，其中板金属基材的下表面被半蚀刻以形成凹槽。 绝缘填充材料填充在半蚀刻槽中。 板金属基材的上表面被半刻蚀以形成芯片焊盘和多排引线。 封装第一个IC芯片，第二个IC芯片，焊料凸块，底部填充材料和金属线，以形成基于多行QFN封装类型的FCoC封装阵列。 锯切和分离FCoC封装阵列，并形成FCoC封装单元。

公开(公告)号：US20050013019A1

公开(公告)日：2005-01-20

申请号：US10722603

申请日：2003-11-28

申请人： Chung-Yang Tseng ,  Shih-Chin Gong ,  Reuy-Shing Huang ,  Tong-An Lee ,  Kuo-Chung Chan ,  Hung-Dar Wang

发明人： Chung-Yang Tseng ,  Shih-Chin Gong ,  Reuy-Shing Huang ,  Tong-An Lee ,  Kuo-Chung Chan ,  Hung-Dar Wang

IPC分类号： G02B7/02 ,  H01L21/18 ,  H01L21/76

CPC分类号： B81C3/002 ,  H01L21/187 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01322 ,  Y10S438/928 ,  Y10S438/975 ,  Y10S438/977

摘要： A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.

摘要翻译： 在粘合后保持晶片的光刻精密对准的方法，其中在对应于在底部晶片上制成的对准标记的位置处在顶部晶片的后表面处形成两个空腔。 两个腔的深度都比最终膜结构深。 然后将顶部晶片结合到已经具有对准标记和微结构的底部晶片。 退火该接合晶片以增强其结合强度。 之后，施加变薄处理直到顶部晶片的厚度减小到比腔深度更薄，使得对准标记出现在顶部晶片空腔中，从而用作任何曝光设备的对准标记。

公开(公告)号：US09397068B2

公开(公告)日：2016-07-19

申请号：US14354583

申请日：2012-12-04

申请人： Fei Qin ,  Guofeng Xia ,  Tong An ,  Wei Wu ,  Chengyan Liu ,  Wenhui Zhu

发明人： Fei Qin ,  Guofeng Xia ,  Tong An ,  Wei Wu ,  Chengyan Liu ,  Wenhui Zhu

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/52 ,  H01L23/28 ,  H01L23/498 ,  H01L23/31 ,  H01L25/03

CPC分类号： H01L24/85 ,  H01L21/4821 ,  H01L21/4828 ,  H01L21/56 ,  H01L21/561 ,  H01L23/142 ,  H01L23/28 ,  H01L23/3121 ,  H01L23/49544 ,  H01L23/49575 ,  H01L23/49861 ,  H01L23/52 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L25/03 ,  H01L2224/16245 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/48247 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2224/05599

摘要： A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

摘要翻译： 提供了一种基于多行四方扁平无引线（QFN）封装的封装封装（PiP）电子器件的制造方法，其中板金属基材的下表面被半蚀刻以形成凹槽。 绝缘填充材料填充在半蚀刻槽中。 板金属基材的上表面被半刻蚀以形成芯片焊盘和多排引线。 用于引线接合的封装IC芯片，粘合材料，金属线，芯片焊盘和多个引线，以形成作为内部封装的多行QFN封装。 在芯片的第一个金属材料层引脚上的倒装芯片接合IC芯片与焊料凸块。 使用焊料凸块封装IC芯片，多行QFN封装，粘合剂材料，并形成PiP电子器件阵列。 锯切和分离PiP电子器件阵列，形成PiP电子器件单元。

公开(公告)号：US06967145B2

公开(公告)日：2005-11-22

申请号：US10722603

申请日：2003-11-28

申请人： Chung-Yang Tseng ,  Shih-Chin Gong ,  Reuy-shing Huang ,  Tong-An Lee ,  Kuo-Chung Chan ,  Hung-Dar Wang

发明人： Chung-Yang Tseng ,  Shih-Chin Gong ,  Reuy-shing Huang ,  Tong-An Lee ,  Kuo-Chung Chan ,  Hung-Dar Wang

IPC分类号： G02B7/02 ,  H01L21/18 ,  H01L21/76

CPC分类号： B81C3/002 ,  H01L21/187 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/83894 ,  H01L2924/01322 ,  Y10S438/928 ,  Y10S438/975 ,  Y10S438/977

摘要： A method of maintaining photolithographic precision alignment for a wafer after being bonded, wherein two cavities are formed at the rear surface of a top wafer at the position corresponding to alignment marks made on a bottom wafer. The depth of both cavities is deeper than that of a final membrane structure. The top wafer is then bonded to the bottom wafer which already has alignment marks and a microstructure. This bonded wafer is annealed to intensify its bonding strength. After that, a thinning process is applied until the thickness of the top wafer is reduced to thinner than the cavity depth such that the alignment marks are emerged in the top wafer cavities thereby serving as alignment marks for any exposure equipment.