公开(公告)号：US5674777A

公开(公告)日：1997-10-07

申请号：US572495

申请日：1995-12-14

申请人： Tung-Po Chen ,  Tan-Fu Lei ,  Chun-Yen Chang

发明人： Tung-Po Chen ,  Tan-Fu Lei ,  Chun-Yen Chang

IPC分类号： H01L21/225 ,  H01L21/20

CPC分类号： H01L21/2254 ,  Y10S148/034 ,  Y10S148/061 ,  Y10S148/144 ,  Y10S148/152

摘要： The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).

摘要翻译： 本发明涉及一种制造具有硼扩散源层的硅电子器件的方法，包括以下步骤：a）提供硅衬底; b）在所述硅衬底上沉积硅层; 以及c）在所述硅层上生长作为所述硼扩散源的硅 - 硼二元化合物层。 当通过根据本发明的UHV / CVD工艺形成Si-B层时，Si-B二元化合物层中的硼浓度将非常高（高达1×10 21至5×10 22原子/ cm 3）。

公开(公告)号：US5943560A

公开(公告)日：1999-08-24

申请号：US635016

申请日：1996-04-19

申请人： Chun-Yen Chang ,  Tan-Fu Lei ,  Hsiao-Yi Lin ,  Juing-Yi Cheng

发明人： Chun-Yen Chang ,  Tan-Fu Lei ,  Hsiao-Yi Lin ,  Juing-Yi Cheng

IPC分类号： H01L21/205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/336

CPC分类号： H01L29/66757 ,  H01L21/0242 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66742 ,  H01L21/2807 ,  H01L21/30625

摘要： Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si.sub.1-x -Ge.sub.x) thin film transistors at low temperature and low thermal budget. Poly-Si and poly-Si.sub.1-x -Ge.sub.x can be deposited by UHV/CVD without any anneal step. And due to the ultra low base pressure and ultraclean growth environment, the As-deposited poly films have low defect densities. However, the surface morphology retards the usage of the fabricating top-gate poly TFT's. In this invention, the CMP system is used for improving the surface morphology, high performance poly-Si and poly-Si.sub.1-x -Ge.sub.x TFT's can be obtained.

摘要翻译： 在能够制造多晶硅（poly-Si）和多晶硅 - 锗（poly-Si1-x-Gex）薄膜晶体管的方法中使用超高真空化学气相沉积（UHV / CVD）和化学机械抛光（CMP） 在低温和低热预算。 Poly-Si和poly-Si1-x-Gex可以通过UHV / CVD进行沉积，无需任何退火步骤。 并且由于超低的基础压力和超高的生长环境，沉积的多晶膜具有低的缺陷密度。 然而，表面形态阻碍了制造顶栅多晶硅TFT的使用。 在本发明中，CMP系统用于改善表面形态，可以获得高性能的多晶硅和多晶Si1-x-Gex TFT。

公开(公告)号：US06551972B1

公开(公告)日：2003-04-22

申请号：US09462464

申请日：2000-04-28

申请人： Tan-Fu Lei ,  Tien-Sheng Chao ,  Ming-Chi Liaw

发明人： Tan-Fu Lei ,  Tien-Sheng Chao ,  Ming-Chi Liaw

IPC分类号： C11D326

CPC分类号： H01L21/02052

摘要： A solution for cleaning silicon semiconductors or silicon oxides comprising H2O2, NH4OH and at least one component A selected from the group consisting of fluoro-containing compounds and other ammonium salts than NH4OH, wherein the weight ratio of H2O2 to H2O is between 1:5 and 1:50, the weight ratio of NH4OH to H2O is between 1:5 and 1:50, and the molar ratio of component A to NH4OH is between 1:10 and 1:5000 is disclosed. The solution can achieve the efficacy equivalent to that of the conventional RCA two-step cleaning solution within a shorter time by one step and effectively remove contaminants such as organics, dust and metals from the surfaces of silicon semiconductors and silicon oxides without using strong acids such as HCl and H2SO4.

摘要翻译： 一种用于清洗硅半导体或氧化硅的溶液，其包含H 2 O 2，NH 4 OH和至少一种选自含NH 4 OH的含氟化合物和其它铵盐的组分A，其中H 2 O 2与H 2 O的重量比为1:5至 1:50，NH4OH与H2O的重量比为1:5至1:50，组分A与NH 4 OH的摩尔比为1:10至1:5000之间。 该溶液可以在较短时间内达到与常规RCA两步清洗溶液相当的功效，并可有效去除硅半导体和氧化硅表面的有机物，灰尘和金属等杂质，而无需使用强酸 作为HCl和H 2 SO 4。

公开(公告)号：US5567638A

公开(公告)日：1996-10-22

申请号：US490401

申请日：1995-06-14

申请人： Yung-Hao Lin ,  Chao-Sung Lai ,  Chung-Len Lee ,  Tan-Fu Lei

发明人： Yung-Hao Lin ,  Chao-Sung Lai ,  Chung-Len Lee ,  Tan-Fu Lei

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/265

CPC分类号： H01L29/4916 ,  H01L21/28035 ,  H01L21/28061 ,  H01L29/4925

摘要： A method for suppressing boron penetration in a PMOS with a nitridized polysilicon gate includes steps of 1) growing a layer of gate oxide on a substrate, 2) forming at least one first polysilicon layer on the gate oxide layer, 3) nitridizing the first polysilicon layer, 4) forming a second polysilicon layer on the first polysilicon layer; and 5) implanting B-containing ions into the first and second polysilicon layers for constructing a PMOS structure wherein the nitridizing step suppresses a boron ion from penetration into the substrate. The present invention is characterized in nitridation on a polysilicon gate instead of a gate oxide which can effectively suppress boron penetration, avoid drawbacks resulting from nitridizing a gate oxide, and moreover, improve the reliability of the device owing to the slight nitridation effect in the polysilicon gate and the gate oxide.

摘要翻译： 一种抑制具有氮化多晶硅栅极的PMOS中的硼渗透的方法包括以下步骤：1）在衬底上生长栅极氧化层，2）在栅极氧化物层上形成至少一个第一多晶硅层，3）使第一多晶硅氮化 4）在第一多晶硅层上形成第二多晶硅层; 以及5）将含B离子注入到第一和第二多晶硅层中以构成PMOS结构，其中氮化步骤抑制硼离子渗透到基底中。 本发明的特征在于在多晶硅栅极上进行氮化，而不是可以有效抑制硼渗透的栅极氧化物，避免由于氮化栅极氧化物而导致的缺陷，而且由于多晶硅中的轻微的氮化作用，提高了器件的可靠性 栅极和栅极氧化物。

公开(公告)号：US5429966A

公开(公告)日：1995-07-04

申请号：US96505

申请日：1993-07-22

申请人： Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

发明人： Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/265

CPC分类号： H01L21/28211 ,  H01L29/51 ,  Y10S438/964

摘要： Disclosed is a thin textured tunnel oxide prepared by thermal oxidation of a thin polysilicon film on Si substrate. Due to the rapid diffusion of oxygen through grain boundries of the thin polysilicon film into the Si substrate and the enhanced oxidation rate at grain boundries, a textured Si/SiO.sub.2 interface is obtained. The textured Si/SiO.sub.2 interface results in localized high fields and causes a much higher electron injection rate. EEPROM memory cells having the textured Si/SiO.sub.2 exhibit a lower electron trapping rate and a lower interface state generation rate even under high field operation.

摘要翻译： 公开了通过Si衬底上的薄多晶硅膜的热氧化制备的薄纹理隧道氧化物。 由于氧通过薄多晶硅膜的晶界快速扩散到Si衬底中，并且在晶界处提高了氧化速率，因此获得了织构化的Si / SiO 2界面。 纹理化的Si / SiO 2界面导致局部高场并导致高得多的电子注入速率。 具有织构化的Si / SiO 2的EEPROM存储单元即使在高场操作下也表现出较低的电子俘获速率和较低的界面状态产生速率。

公开(公告)号：US06605230B1

公开(公告)日：2003-08-12

申请号：US09155181

申请日：1999-03-26

申请人： Ming-Chi Liaw ,  Tien-Sheng Chao ,  Tan-Fu Lei

发明人： Ming-Chi Liaw ,  Tien-Sheng Chao ,  Tan-Fu Lei

IPC分类号： H01L214757

CPC分类号： H01L21/02071 ,  G03F7/423 ,  H01L21/31133

摘要： The present invention relates to a novel process for removing sidewall residue after dry-etching process. Conventionally, after dry-etching, photoresist and sidewall residues are removed by ozone ashing and hot sulfuric acid. Normally, they are hard to be removed completely. It was found in the present invention that the addition of fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in sulfuric acid results in complete removal of photoresist and sidewall residue without the need for stripper. The process is simple and does not affect the original procedures or the other films on the substrate. The present invention also relates to a novel solution for removing sidewall residue after dry-etching, which comprises sulfuric acid and a fluorine-containing compound, preferably hydrogen fluoride and ammonium fluoride, in the range of from 10:1 to 1000:1 by weight.

摘要翻译： 本发明涉及一种在干蚀刻工艺之后去除侧壁残留物的新方法。 通常，干蚀刻后，通过臭氧灰化和热硫酸除去光致抗蚀剂和侧壁残留物。 通常，它们很难被完全清除。 在本发明中发现，在硫酸中加入含氟化合物，优选氟化氢和氟化铵，导致完全去除光致抗蚀剂和侧壁残留物，而不需要剥离剂。 该方法简单，不影响原始程序或其他底物上的膜。 本发明还涉及一种用于在干法蚀刻之后除去侧壁残留物的新型溶液，其包含硫酸和含氟化合物，优选氟化氢和氟化铵，重量比为10:1至1000:1 。

公开(公告)号：US06180419B2

公开(公告)日：2001-01-30

申请号：US08715934

申请日：1996-09-19

申请人： Hsiao-Yi Lin ,  Tan-Fu Lei ,  Ci-Lin Pan ,  Chun Y. Chang ,  Jz-Jan Jeng

发明人： Hsiao-Yi Lin ,  Tan-Fu Lei ,  Ci-Lin Pan ,  Chun Y. Chang ,  Jz-Jan Jeng

IPC分类号： H01L2100

CPC分类号： G01R33/07

摘要： A method for manufacturing a magnetic field transducing device is provided which includes (a) providing a substrate, (b) subjecting the substrate to a semiconductor device fabricating process in order to obtain a magnetic field transducer, (c) forming an oxide over the magnetic field transducer and (d) covering a magnetic film on the oxide in order to obtain the magnetic field transducing device. The semiconductor device fabricating process also includes (b1) utilizing a mask photolithography etching process to form an annular groove on the substrate, (b2) covering a first insulating layer on the substrate and using a second mask photolithography etching process to form a plurality of diffusing openings on the first insulation layer, (b3) forming extrinsic semiconductor region on the substrate exposed by the plurality of diffusing openings, (b4) forming a second insulation layer on the substrate, (b5) utilizing a third mask photolithography etching process to form a plurality of contacts on the extrinsic semiconductor region, and (b6) forming a conductor on the substrate in order to form a connecting line. The magnetic film is preferably made of Ni and Co.

摘要翻译： 提供了一种用于制造磁场换能装置的方法，该方法包括：（a）提供一基板，（b）使基板经受半导体器件制造工艺以获得一磁场换能器;（c） 场传感器和（d）覆盖氧化物上的磁性膜以获得磁场换能装置。 半导体器件制造工艺还包括（b1）利用掩模光刻蚀刻工艺在衬底上形成环形沟槽，（b2）覆盖衬底上的第一绝缘层，并使用第二掩模光刻蚀刻工艺形成多个扩散 在第一绝缘层上的开口，（b3）在由多个扩散开口暴露的衬底上形成非本征半导体区域，（b4）在衬底上形成第二绝缘层，（b5）利用第三掩模光刻蚀刻工艺形成 在外部半导体区域上的多个触点，以及（b6）在基板上形成导体以形成连接线。 磁性膜优选由Ni和Co制成

公开(公告)号：US20090230400A1

公开(公告)日：2009-09-17

申请号：US12198081

申请日：2008-08-25

申请人： Chia-Wen Chang ,  Jiun-Jia Huang ,  Tzu-Heng Chang ,  Tan-Fu Lei ,  Szu-Fen Chen

发明人： Chia-Wen Chang ,  Jiun-Jia Huang ,  Tzu-Heng Chang ,  Tan-Fu Lei ,  Szu-Fen Chen

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/66757 ,  H01L29/66787 ,  H01L29/785

摘要： A method for fabricating a thin film transistor is described. The method includes: providing a substrate; forming a sacrificial layer on the substrate; forming a polysilicon pattern layer on the substrate to surround the sacrificial layer; forming a gate insulation layer to cover at least the polysilicon pattern layer; forming a gate pattern on the gate insulation layer above the polysilicon pattern layer; forming a source region, a drain region, and an active region in the polysilicon pattern layer, wherein the active region is between the source region and the drain region; forming a passivation layer to cover the gate pattern and a portion of the gate insulation layer; forming a source conductive layer and a drain conductive layer on the passivation layer, wherein the source conductive layer and the drain conductive layer are electrically connected to the source region and the drain region of the polysilicon pattern layer respectively.

摘要翻译： 对薄膜晶体管的制造方法进行说明。 该方法包括：提供衬底; 在所述基板上形成牺牲层; 在所述衬底上形成多晶硅图案层以围绕所述牺牲层; 形成栅绝缘层以至少覆盖所述多晶硅图案层; 在多晶硅图案层上方的栅极绝缘层上形成栅极图案; 在所述多晶硅图案层中形成源极区，漏极区和有源区，其中所述有源区在所述源极区和所述漏极区之间; 形成钝化层以覆盖所述栅极图案和所述栅极绝缘层的一部分; 在所述钝化层上形成源极导电层和漏极导电层，其中所述源极导电层和所述漏极导电层分别电连接到所述多晶硅图案层的源极区域和所述漏极区域。

公开(公告)号：US5347161A

公开(公告)日：1994-09-13

申请号：US939244

申请日：1992-09-02

申请人： Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

发明人： Shye-Lin Wu ,  Chung-Len Lee ,  Tan-Fu Lei

IPC分类号： H01L21/225 ,  H01L21/329 ,  H01L29/45 ,  H01L29/861 ,  H01L23/48 ,  H01L29/46

CPC分类号： H01L29/66128 ,  H01L21/2257 ,  H01L29/456 ,  H01L29/8611

摘要： A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.

摘要翻译： 一种工艺用于制造具有发射极接触p-n结的二极管。 在p型硅衬底上形成一堆n +型多晶硅层。 在相应制造的二极管中，在n +型多晶硅层和p型衬底之间形成的自然氧化物层易于破裂，并且在其之间形成更厚的外延层。 p-n结的厚度为0.05-0.2μm。 由于二极管被反向偏置，例如在-5V，漏电流可能小于1 n ANGSTROM / cm2。 反向偏压击穿电压可能大于-100V。正向偏置时，二极管的理想系数接近于1。